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前言

笔试题型：选择题（15个） + 简答题（3个）
笔试平台：Showmebug
笔试时间：1h

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一、选择题

1. [多选]在Verilog里面，==操作的可能的结果是

A. 1
B. Z
C. 0
D. X

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2. [单选]在Verilog里面,如果想在逻辑中引入延时，可以使用

A. XOR gate
B. Inverter
C. Flip-flops
D. Buffer

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3. [单选]如果X= 4’b1100,那么以下哪条语句会被执行?

wire [3:0] x;
always @(...) begincase (1'b1)x[0]: SOMETHING1;x[1]: SOMETHING2;x[2]: SOMETHING3;x[3]: SOMETHING4;endcase
end

A. SOMETHING4
B. SOMETHING3
C.SOMETHING2
D. SOMETHING1

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4. [多选]在Verilog里面，以下哪些对于操作符的描述是正确的

A. A logical “or” is performed by writing “C=A||B”
B.”~“performs logical negation while”!" performs bitwise negation
C.The two types of “or” operators are “logical” and “bitwise.’
D.The 'shift right” (>>) operator inserts zeros on the left et d of its argument

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5. [单选]在Verilog里面，如果设置timescale，以便能够实现0.3ps的delay，以及仿真的步长是1ps

A. timescale 1ps/1ps
B. timescale 100ps/1ps
C. timescale 10ps/1ps
D. timescale 1ps/0.1ps

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6. [单选]扫描链在以下哪个步骤被插入?

A. RTL design stage
B. After Clock Tree Synthesi
C. After Place & Route
D. After Synthesis

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7. [单选]在Verilog里面，以下哪些描述对于non-blocking assignment是正确的

A. Evaluates all RHS for the current time unit and assign to LHS at the current time
B. Both of the above options are correct, depending on the specific case
C. None of the options are correct
D. Evaluates all RHS(right hand side) for the current time unit and assign to LHS(left hand side) at the end of time unit

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8. [单选]一个元件的时主要取决于以下哪些因素

A Input transition & output transition
B. Input load & output load
C. Input transition & output load
D. Output transition & input load

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9. [单选]如果A=4’b0011, B=3’b110, C=4’b1010,那么表达式下面表达式的结果为？

{2{~|A}} | (B[2:1] & C[1:0])

A. 10
B. 11
C. 00
D. 01

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10. [单选]在Verilog里面，以下哪个命令可以结束当前的仿真

A. $end
B. $close
C. $finish
D. $stop

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11. [单选]在Verilog里面,以下哪个操作符可以触发一个事件

A. -->
B. ==
C. @
D. =>

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12. [单选]在Verilog的描述里面，#10 clock = ~clock，对应的clock的周期是的多少

A. 5
B. None
C.10
D. 20

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13、 [多选] 在verilog里面，@posedge包含下面哪些情况

A. 1->0
B. 0->1, x, or z
C. x->1
D. z->1, or x

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14. [多选]在Verilog里面，以下哪些对于多维数组的初始化是正确的

A. a[0][0] =1’b0
B. All of the options are correct
C. reg [7:0] a[15:0] =16’h0000
D. a[0] =16’h0000

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15. [多选]在Verilog里面，对于赋值中出现位宽不匹配的后果的描述正确的是（

A. Can result in simulation error
B. May cause unpredictable result in comparing logic
C. No effect
D. Can result in synthesis error

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二、问答题

1、UVM中，active mode和passive mode有什么区别

2、请用任何你熟悉的脚本语言，比如Perl,python, tcl/tk或者shell脚本从’013adbGh’中检测出字符串’adb’，返回1，如果检测到对应的字符串，否则返回’0’.

3、下面是一个4位半加器的实现，以及一个用verilog编写的testbend以便实现自动化验证。请补充完testbendh里面缺少的代码

module add 4(input[3:0] in1,in2;output[3:0] sum,output cout
);assign{coutsum}= in1+in2;
endmodulemodule tb_adder_40;logic[3:0] in1;logic[3:0] in2;logic cout;logic[3:0] sum;logic[4:0]exp_sum;bit chk_status=0;initial beginin1<=3'b0;in2<=3b0;for(int i=0; i<16; i++) beginfor(int j=0; j<16;j++) begin#1;in1=i;in2=j;chk_status=check_sum(in1,in2,{cout,sum});if(chk_status == 0) begin$display("Test Fail!);$finish;endendend$display(Test PASS!);
endfunction bit check_sum(logic [3:0] in1,logic [3:0] in2, logic[4:0] exp_sum);//补充代码return comp_result;
endfunctionadd_4 u_add_4(.in1(in1),.in2(in2),.sum(sum),.cout(cout)
);
endmodule