本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益

题目链接：Mux2to1 - HDLBits

module top_module( input a, b, sel,output out ); assign out = sel ? b : a ; 
endmodule

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题目链接：Mux2to1v - HDLBits

module top_module( input [99:0] a, b,input sel,output [99:0] out );assign out = sel ? b : a ; 
endmodule

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题目链接：Mux9to1v - HDLBits

module top_module( input [15:0] a, b, c, d, e, f, g, h, i,input [3:0] sel,output reg [15:0] out );always @(*) begincase (sel)0 : out = a ; 1 : out = b ; 2 : out = c ; 3 : out = d ; 4 : out = e ; 5 : out = f ; 6 : out = g ; 7 : out = h ; 8 : out = i ; default : out = '1 ; // Set all bits to 1endcaseendendmodule

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题目链接：Mux256to1 - HDLBits

module top_module( input [255:0] in,input [7:0] sel,output out );assign out = in[sel] ;
endmodule

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题目链接：Mux256to1v - HDLBits

module top_module( input [1023:0] in,input [7:0] sel,output reg [3:0] out );always @(*) begininteger i ; for (i = 0 ; i <= 3 ; i = i + 1)out[i] = in[sel * 4 + i] ;endendmodule