ProASIC®3 Flash Family FPGAs with Optional Soft ARM® Support

Features and Benefits
High Capacity
• 30 k to 1 Million System Gates
• Up to 144 kbits of True Dual-Port SRAM
• Up to 300 User I/Os
Reprogrammable Flash Technology
• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
• Live at Power-Up (LAPU) Level 0 Support
• Single-Chip Solution
• Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
• 1 kbit of FlashROM with Synchronous Interfacing High Performance
• 350 MHz System Performance
• 3.3 V, 66 MHz 64-Bit PCI (except A3P030)
In-System Programming (ISP) and Security
• Secure ISP Using On-Chip 128-Bit Advanced Encryption
Standard (AES) Decryption (except A3P030 and ARM®-
enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)
• FlashLock® to Secure FPGA Contents
Low Power
• Core Voltage for Low Power
• Support for 1.5-V-Only Systems
• Low-Impedance Flash Switches
High-Performance Routing Hierarchy
• Segmented, Hierarchical Routing and Clock Structure
• Ultra-Fast Local and Long-Line Network
• Enhanced High-Speed, Very-Long-Line Network
• High-Performance, Low-Skew Global Network
• Architecture Supports Ultra-High Utilization
Advanced I/O
• 700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
• Bank-Selectable I/O Voltages—Up to 4 Banks per Chip
• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /
2.5 V / 1.8 V / 1.5 V,3.3 V PCI / 3.3 V PCI-X (except
A3P030), and LVCMOS 2.5 V / 5.0 V Input
• Differential I/O Standards: LVPECL, LVDS, BLVDS, and
M-LVDS (A3P250 and above)
• I/O Registers on Input, Output, and Enable Paths
• Hot-Swappable and Cold Sparing I/Os (A3P030 only)
• Programmable Output Slew Rate (except A3P030) and
Drive Strength
• Weak Pull-Up/Down
• IEEE 1149.1 (JTAG) Boundary Scan Test
• Pin-Compatible Packages Across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL (except A3P030)
• Six CCC Blocks, One with an Integrated PLL
• Configurable Phase-Shift, Multiply/Divide, Delay
Capabilities and External Feedback, Multiply/Divide,
Delay Capabilities, and External Feedback
• Wide Input Frequency Range (1.5 MHz to 350 MHz)
• CoreMP7Sd (with debug) and CoreMP7S (without debug
SRAMs and FIFOs (except A3P030)
• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2,
×4, ×9, and ×18 Organizations Available)
• True Dual-Port SRAM (except ×18)
• 24 SRAM and FIFO Configurations with Synchronous
Operation up to 350 MHz
Soft ARM7™ Core Support in M7 ProASIC3 Devices
• CoreMP7Sd (with debug) and CoreMP7S (without
debug)

Introduction and Overview
General Description
ProASIC3, the third-generation family of Actel Flash
FPGAs, offers performance, density, and features beyond
those of the ProASICPLUS® family. Nonvolatile Flash
technology gives ProASIC3 devices the advantage of
being a secure, low-power, single-chip solution that is
live at power-up (LAPU). ProASIC3 is reprogrammable
and offers time-to-market benefits at an ASIC-level unit
cost. These features enable designers to create high density
systems using existing ASIC or FPGA design flows
and tools.
ProASIC3 devices offer 1 kbit of on-chip,
reprogrammable, nonvolatile FlashROM storage as well
as clock conditioning circuitry based on an integrated
phase-locked loop (PLL). The A3P030 device has no PLL or
RAM support. ProASIC3 devices have up to 1 million
system gates, supported with up to 144 kbits of true
dual-port SRAM and up to 288 user I/Os.
ProASIC3 devices support the ARM7 soft IP core in
devices with at least 250 k system gates. The ARMenabled
devices have Actel ordering numbers that begin
with M7A3P and do not support AES decryption.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost,
performance, and ease of use. Unlike SRAM-based
FPGAs, Flash-based ProASIC3 devices allow all
functionality to be live at power-up; no external boot
PROM is required. On-board security mechanisms
prevent access to all the programming information and
enable secure remote updates of the FPGA logic.
Designers can perform secure remote in-system
reprogramming to support future design iterations and
field upgrades with confidence that valuable intellectual
property (IP) cannot be compromised or copied. Secure
ISP can be performed using the industry-standard AES
algorithm. The ProASIC3 family device architecture
mitigates the need for ASIC migration at higher user
volumes. This makes the ProASIC3 family a cost-effective
ASIC replacement solution, especially for applications in
the consumer, networking/ communications, computing,
and avionics markets.
Security
The nonvolatile, Flash-based ProASIC3 devices do not
require a boot PROM, so there is no vulnerable external
bitstream that can be easily copied. ProASIC3 devices
incorporate FlashLock, which provides a unique
combination of reprogrammability and design security
without external overhead, advantages that only an
FPGA with nonvolatile Flash programming can offer.
ProASIC3 devices utilize a 128-bit Flash-based lock and a
separate AES key to secure programmed intellectual
property and configuration data. In addition, all
FlashROM data in ProASIC3 devices can be encrypted
prior to loading, using the industry-leading AES-128
(FIPS192) bit block cipher encryption standard. The AES
standard was adopted by the National Institute of
Standards and Technology (NIST) in 2000 and replaces
the 1977 DES standard. ProASIC3 devices have a built-in
AES decryption engine and a Flash-based AES key that
make them the most comprehensive programmable logic
device security solution available today. ProASIC3 devices
with AES-based security allow for secure, remote field
updates over public networks such as the Internet, and
ensure that valuable IP remains out of the hands of
system overbuilders, system cloners, and IP thieves. The
contents of a programmed ProASIC3 device cannot be
read back, although secure design verification is possible.
ARM-enabled ProASIC3 devices do not support usercontrolled
AES security mechanisms. Since the ARM core
must be protected at all times, AES encryption is always
on for the core logic, so bitstreams are always encrypted.
There is no user access to encryption for the FlashROM
programming data.
Security, built into the FPGA fabric, is an inherent
component of the ProASIC3 family. The Flash cells are
located beneath seven metal layers, and many device
design and layout techniques have been used to make
invasive attacks extremely difficult. The ProASIC3 family,
with FlashLock and AES security, is unique in being highly
resistant to both invasive and noninvasive attacks. Your
valuable IP is protected and secure, making remote ISP
possible. An ProASIC3 device provides the most
impenetrable security for programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information
in on-chip Flash cells. Once programmed, the
configuration data is an inherent part of the FPGA
structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based
FPGAs). Therefore, Flash-based ProASIC3 FPGAs do not
require system configuration components such as
EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs
and PCB area, and increases security and system
reliability.
Live at Power-Up
The Actel Flash-based ProASIC3 devices support Level 0
of the LAPU classification standard. This feature helps in
system component initialization, execution of critical
tasks before the processor wakes up, setup and
configuration of memory blocks, clock generation, and
bus activity management. The LAPU feature of Flashbased
ProASIC3 devices greatly simplifies total system
design and reduces total system cost, often eliminating
the need for CPLDs and clock generation PLLs that are
used for these purposes in a system. In addition, glitches
and brownouts in system power will not corrupt the
ProASIC3 device’s Flash configuration, and unlike SRAMbased
FPGAs, the device will not have to be reloaded
when system power is restored. This enables the
reduction or complete removal of the configuration
PROM, expensive voltage monitor, brownout detection,
and clock generator devices from the PCB design. Flashbased
ProASIC3 devices simplify total system design and
reduce cost and design risk while increasing system
reliability and improving system initialization time.
Firm Errors
Firm errors occur most commonly when high-energy
neutrons, generated in the upper atmosphere, strike a
configuration cell of an SRAM FPGA. The energy of the
collision can change the state of the configuration cell
and thus change the logic, routing, or I/O behavior in an
unpredictable way. These errors are impossible to
prevent in SRAM FPGAs. The consequence of this type of
error can be a complete system failure. Firm errors do
not exist in the configuration memory of ProASIC3 Flashbased
FPGAs. Once it is programmed, the Flash cell
configuration element of ProASIC3 FPGAs cannot be
altered by high-energy neutrons and is therefore
immune to them. Recoverable (or soft) errors occur in
the user data SRAM of all FPGA devices. These can easily
be mitigated by using error detection and correction
(EDAC) circuitry built into the FPGA fabric.
Low Power
Flash-based ProASIC3 devices exhibit power
characteristics similar to an ASIC, making them an ideal
choice for power-sensitive applications. ProASIC3 devices
have only a very limited power-on current surge and no
high-current transition period, both of which occur on
many FPGAs.
ProASIC3 devices also have low dynamic power
consumption to further maximize power savings.
Advanced Flash Technology
The ProASIC3 family offers many benefits, including
nonvolatility and reprogrammability through an
advanced Flash-based, 130-nm LVCMOS process with
seven layers of metal. Standard CMOS design techniques
are used to implement logic and control functions. The
combination of fine granularity, enhanced flexible
routing resources, and abundant Flash switches allows
for very high logic utilization without compromising
device routability or performance. Logic functions within
the device are interconnected through a four-level
routing hierarchy.
Advanced Architecture
The proprietary ProASIC3 architecture provides
granularity comparable to standard-cell ASICs. The
ProASIC3 device consists of five distinct and
programmable architectural features (Figure 1 and
Figure 2 on page 7):
• FPGA VersaTiles
• Dedicated FlashROM
• Dedicated SRAM/FIFO memory1
• Extensive CCCs and PLLs1
• Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each
VersaTile can be configured as a three-input logic
function, a D-flip-flop (with or without enable), or a
latch by programming the appropriate Flash switch
interconnections. The versatility of the ProASIC3 core tile
as either a three-input lookup table (LUT) equivalent or
as a D-flip-flop/latch with enable allows for efficient use
of the FPGA fabric. The VersaTile capability is unique to
the Actel ProASIC family of third-generation architecture
Flash FPGAs. VersaTiles are connected with any of the
four levels of routing hierarchy. Flash switches are
distributed throughout the device to provide
nonvolatile, reconfigurable interconnect programming.
Maximum core utilization is possible for virtually any
design.
In addition, extensive on-chip programming circuitry
allows for rapid, single-voltage (3.3 V) programming of
ProASIC3 devices via an IEEE 1532 JTAG interface.