输入序列连续的序列检测

题目描述
请编写一个序列检测模块，检测输入信号a是否满足01110001序列，当信号满足该序列，给出指示信号match。

模块的接口信号图如下：

模块的时序图如下：

`timescale 1ns/1ns
module sequence_detect(input clk,input rst_n,input a,output reg match);parameter idle   = 9'b000000001;parameter state1 = 9'b000000010;parameter state2 = 9'b000000100;parameter state3 = 9'b000001000;parameter state4 = 9'b000010000;parameter state5 = 9'b000100000;parameter state6 = 9'b001000000;parameter state7 = 9'b010000000;parameter state8 = 9'b100000000;reg [0:8] c_state,n_state;//状态转移always@(posedge clk or negedge rst_n)beginif(!rst_n)c_state <= idle;else c_state <= n_state;end//现态和输入决定次态always@(*)begincase(c_state)idle:beginif(a == 1'b0)n_state = state1;elsen_state = idle;endstate1:beginif(a == 1'b1)n_state = state2;elsen_state = state1;endstate2:beginif(a == 1'b1)n_state = state3;elsen_state = state1;endstate3:beginif(a == 1'b1)n_state = state4;elsen_state = state1;endstate4:beginif(a == 1'b0)n_state = state5;elsen_state = idle;endstate5:beginif(a == 1'b0)n_state = state6;elsen_state = idle;endstate6:beginif(a == 1'b0)n_state = state7;elsen_state = idle;endstate7:beginif(a == 1'b1)n_state = state8;elsen_state = state1;endstate8:beginif(a == 1'b1)n_state = idle;elsen_state = state1;enddefault:n_state = idle;endcaseendalways@(posedge clk or negedge rst_n)beginif(!rst_n)match <= 1'b0;else if(c_state == state8)match <= 1'b1;elsematch <= 1'b0;end
endmodule