含有无关项的序列检测

题目描述
请编写一个序列检测模块，检测输入信号a是否满足011XXX110序列（长度为9位数据，前三位是011，后三位是110，中间三位不做要求），当信号满足该序列，给出指示信号match。

程序的接口信号图如下：

程序的功能时序图如下：

`timescale 1ns/1ns
module sequence_detect(input clk,input rst_n,input a,output reg match);parameter idle   = 8'b00000001;parameter state1 = 8'b00000010;parameter state2 = 8'b00000100;parameter state3 = 8'b00001000;parameter state4 = 8'b00010000;parameter state5 = 8'b00100000;parameter state6 = 8'b01000000;parameter state7 = 8'b10000000;reg [0:7] c_state,n_state;reg [0:1] cnt;always@(posedge clk or negedge rst_n)beginif(!rst_n)c_state <= idle;elsec_state <= n_state;endalways@(*)begincase(c_state)idle:beginif(a == 0)n_state = state1;elsen_state = idle;endstate1:beginif(a == 1)n_state = state2;elsen_state = state1;endstate2:beginif(a == 1)n_state = state3;elsen_state = state1;endstate3:beginif(cnt == 2)n_state = state4;elsen_state = state3;endstate4:beginif(a == 1)n_state = state5;elsen_state = state1;endstate5:beginif(a == 1)n_state = state6;elsen_state = state1;endstate6:beginif(a == 0)n_state = state7;elsen_state = idle;endstate7:beginif(a == 1)n_state = idle;elsen_state = state1;enddefault:n_state = idle;endcaseendalways@(posedge clk or negedge rst_n)beginif(!rst_n)cnt <= 2'b0;else if(c_state == state3 && cnt == 2'd3)cnt <= 2'b0;else if(c_state == state3)cnt <= cnt + 1'b1;elsecnt <= 2'b0;endalways@(posedge clk or negedge rst_n)beginif(!rst_n)match <= 1'b0;else if(c_state == state7)match <= 1'b1;elsematch <= 1'b0;end
endmodule