状态机-非重叠的序列检测

题目描述
设计一个状态机，用来检测序列 10111，要求：

1、进行非重叠检测 即101110111 只会被检测通过一次

2、寄存器输出且同步输出结果

注意rst为低电平复位

信号示意图：

`timescale 1ns/1nsmodule sequence_test1(input wire clk  ,input wire rst  ,input wire data ,output reg flag
);
//*************code***********//parameter idle   = 6'b000001;parameter state1 = 6'b000010;parameter state2 = 6'b000100;parameter state3 = 6'b001000;parameter state4 = 6'b010000;parameter state5 = 6'b100000;reg [5:0] c_state,n_state;always@(posedge clk or negedge rst)beginif(!rst)c_state <= idle;elsec_state <= n_state;endalways@(*)begincase(c_state)idle:beginif(data == 1'b1)n_state = state1;elsen_state = idle;endstate1:beginif(data == 1'b0)n_state = state2;elsen_state = idle;endstate2:beginif(data == 1'b1)n_state = state3;elsen_state = idle;endstate3:beginif(data == 1'b1)n_state = state4;elsen_state = idle;endstate4:beginif(data == 1'b1)n_state = state5;elsen_state = idle;endstate5:beginn_state = idle;enddefault:n_state = idle;endcaseendalways@(*)beginif(!rst)flag = 1'b0;else if(c_state == state5)flag = 1'b1;elseflag = 1'b0;end//*************code***********//
endmodule

方法二

reg [4:0]current_state;
reg [4:0]next_state;parameter IDLE = 5'b00001;
parameter s1   = 5'b00010;
parameter s2   = 5'b00100;
parameter s3   = 5'b01000;
parameter s4   = 5'b10000;always@(posedge clk or negedge rst)if(!rst)next_state <= 0;elsenext_state <= current_state;always@(*)case(next_state)IDLE : current_state = data ? s1 : IDLE;s1   : current_state = !data ? s2 : s1;s2   : current_state = data ? s3 : IDLE;s3   : current_state = data ? s4 : s2;s4   : current_state = data ? IDLE : s2;default : current_state = IDLE;endcasealways@(posedge clk or negedge rst)if(!rst)flag <= 0;else if(next_state == s4 && data)flag <= 1;elseflag <= 0;