状态机-重叠序列检测

题目描述
设计一个状态机，用来检测序列 1011，要求：

1、进行重叠检测 即10110111 会被检测通过2次

2、寄存器输出，在序列检测完成下一拍输出检测有效

注意rst为低电平复位

信号示意图

画出状态转移图

`timescale 1ns/1nsmodule sequence_test2(input wire clk  ,input wire rst  ,input wire data ,output reg flag
);
//*************code***********//parameter idle   = 5'b00001;parameter state1 = 5'b00010;parameter state2 = 5'b00100;parameter state3 = 5'b01000;parameter state4 = 5'b10000;reg[4:0] c_state,n_state;always@(posedge clk or negedge rst)beginif(!rst)c_state <= idle;elsec_state <= n_state;endalways@(*)begincase(c_state)idle:beginif(data == 1'b1)n_state = state1;elsen_state = idle;endstate1:beginif(data == 1'b0)n_state = state2;elsen_state = state1;endstate2:beginif(data == 1'b1)n_state = state3;elsen_state = idle;endstate3:beginif(data == 1'b1)n_state = state4;elsen_state = state2;endstate4:beginif(data == 1'b1)n_state = state1;elsen_state = state2;enddefault:n_state = idle;endcaseendalways@(posedge clk or negedge rst)beginif(!rst)flag <= 1'b0;else if(c_state == state4)flag <= 1'b1;elseflag <= 1'b0;end
//*************code***********//
endmodule

方法二

`timescale 1ns/1nsmodule sequence_test2(input wire clk  ,input wire rst  ,input wire data ,output reg flag
);
//*************code***********//parameter S0=0, S1=1, S2=2, S3=3, S4=4;reg [2:0] state, nstate;always@(posedge clk or negedge rst) beginif(~rst)state <= S0;elsestate <= nstate;endalways@(*) beginif(~rst)nstate <= S0;elsecase(state)S0     : nstate <= data? S1: S0;S1     : nstate <= data? S1: S2;S2     : nstate <= data? S3: S0;S3     : nstate <= data? S4: S2;S4     : nstate <= data? S1: S2;default: nstate <= S0;endcaseendalways@(posedge clk or negedge rst) beginif(~rst)flag <= 0;elseflag <= state==S4;end//*************code***********//
endmodule