专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

`timescale 1ns/1nsmodule triffic_light(input rst_n, //异位复位信号，低电平有效input clk, //时钟信号input pass_request,output wire[7:0]clock,output reg red,output reg yellow,output reg green);parameter idle = 0, s1_red = 1, s2_yellow = 2, s3_green = 3 ;reg [7:0] cnt ; reg [1:0] state ; reg p_red, p_yellow, p_green ; //用于缓存信号灯的前一时刻的数值，判断上升沿always @ (posedge clk or negedge rst_n) begin if (~rst_n) begin state <= idle ;p_red <= 0 ;p_green <= 0 ; p_yellow <= 0 ; endelse case(state) idle : begin p_red <= 0 ; p_green <= 0 ; p_yellow <= 0 ; state <= s1_red ; ends1_red : begin p_red <= 1 ; p_green <= 0 ;p_yellow <= 0 ;if (cnt == 3) state <= s2_yellow ; else state <= s1_red ; ends2_yellow : beginp_red <= 0 ; p_green <= 0 ; p_yellow <= 1 ; if (cnt == 3) state <= s3_green ; else state <= s2_yellow ; ends3_green : begin p_red <= 0 ; p_green <= 1 ; p_yellow <= 0 ; if (cnt == 3) state <= s1_red ; else state <= s3_green ;endendcaseendalways @ (posedge clk or negedge rst_n) begin if (~rst_n) cnt <= 10 ; else if (pass_request && green && (cnt > 10)) cnt <= 10 ; else if (~green && p_green) cnt <= 60 ; else if (~yellow && p_yellow) cnt <= 5 ; else if (~red && p_red) cnt <= 10 ; else cnt <= cnt - 1 ; endassign clock = cnt ; always @ (posedge clk or negedge rst_n) begin if (~rst_n) begin yellow <= 0 ; red <= 0 ; green <= 0 ; endelse begin yellow <= p_yellow ; red <= p_red ; green <= p_green ; endendendmodule