专栏前言
本专栏的内容主要是记录本人学习Verilog过程中的一些知识点,刷题网站用的是牛客网
`timescale 1ns/1nsmodule even_div(input wire rst ,input wire clk_in,output wire clk_out2,output wire clk_out4,output wire clk_out8);
//*************code***********//reg out2, out4, out8 ;always @ (posedge clk_in or negedge rst) begin if (~rst) out2 <= 'd0 ; else out2 <= ~out2 ; endalways @ (posedge clk_out2 or negedge rst) begin if (~rst) out4 <= 'd0 ; else out4 <= ~out4 ; endalways @ (posedge clk_out4 or negedge rst) begin if (~rst) out8 <= 'd0 ; else out8 <= ~out8 ; endassign clk_out2 = out2 ; assign clk_out4 = out4 ; assign clk_out8 = out8 ;//*************code***********//
endmodule