【FPGA + 串口】功能完备的串口测试模块，三种模式：自发自收、交叉收发、内源

VIO 控制单元

wire [1:0] mode;vio_uart UART_VIO (.clk(ad9361_l_clk),                // input wire clk.probe_out0(mode)  // output wire [1 : 0] probe_out0
);

将 mode设置为0，是自发自收；
将 mode设置为1，是交叉收发；
将 mode设置为2，是内源；外部串口直接看数据即可；

FPGA 捕获ILA

ila_uart_tx ILA_s (.clk(ad9361_l_clk), // input wire clk.probe0(J1D3_RXD_A1), // input wire [0:0]  probe0  .probe1(J1D6_RXD_A2) // input wire [0:0]  probe1
);

主函数 测试系统

reg [31:0] cnts;always @ (posedge ad9361_l_clk or posedge rst)
beginif(rst)begincnts <= 32'd0;endelse if(cnts == 32'd110000000)begincnts <= 32'd0;    endelsebegincnts <= cnts + 1'b1;end
endreg [7:0] uart_din;
reg uart_din_clk_p;always @ (posedge ad9361_l_clk or posedge rst)
beginif(rst)beginuart_din <= 8'd0;uart_din_clk_p <= 1'b0;endelsebegincase(cnts)32'd1:begin uart_din<=8'hEB;uart_din_clk_p<=1'b1; end32'd2:begin uart_din<=8'hAA;uart_din_clk_p<=1'b1; end32'd3:begin uart_din<=8'hBB;uart_din_clk_p<=1'b1; end32'd4:begin uart_din<=8'h65;uart_din_clk_p<=1'b1; end32'd5:begin uart_din<=8'h00;uart_din_clk_p<=1'b1; end32'd6:begin uart_din<=8'h00;uart_din_clk_p<=1'b0; enddefault:begin uart_din<=uart_din;uart_din_clk_p<=uart_din_clk_p;  endendcaseend
end
wire send_uart;
uart_com_send_one_bit
#(.FRAME_LENGTH(16'd5                   )//多少个字节。
)UART_SEND(.clk(ad9361_l_clk                     ),.rst(rst                              ),.CLK_FRE(32'd143936068                ),//4*串口波特率*2^32/clk;,4倍于串口速率较合理，从FIFO中读数据，然后发送。 115200@110M.din(uart_din                         ),.din_clk_p(uart_din_clk_p             ), .send_uart(send_uart                  ),   //RS422，RS232,RS485输出信号，默认1，即为高电平.send_uart_en(                        ) //RS485时才用到，FPGA发送至外部信号时该使能信号为1，不发送时该使能信号为0，注意外部使能信号的高低与硬件表述该信号的内容一致!!!
);reg J1D1_TXD_Y1;
reg J1D4_TXD_Y2;always @ (posedge ad9361_l_clk or posedge rst)
beginif(rst)beginJ1D1_TXD_Y1 <= 1'b1;J1D4_TXD_Y2 <= 1'b1;endelsebegincase(mode)2'd0:begin J1D1_TXD_Y1<=J1D3_RXD_A1;J1D4_TXD_Y2<=J1D6_RXD_A2; end2'd1:begin J1D1_TXD_Y1<=J1D6_RXD_A2;J1D4_TXD_Y2<=J1D3_RXD_A1; end2'd2:begin J1D1_TXD_Y1<=send_uart;  J1D4_TXD_Y2<=send_uart;   enddefault:begin J1D1_TXD_Y1<=J1D3_RXD_A1;J1D4_TXD_Y2<=J1D6_RXD_A2;  endendcaseend
end

总结

通过三种模式的测量，可以精确的测量串口是否通，出故障，也可以判断出 是TX还是RX。

该模块可以在任何一个FPGA中运行，欢迎交流。