使用FPGA实现超前进位加法器

介绍

前面已经向大家介绍过8位逐位进位加法器了，今天向大家介绍4位超前进位加法器。

对于逐位进位加法器来说，计算任意一位的加法运算时，必须等到低位的加法运算结束送来进位才能运行。这种加法器结构简单，但是运算慢。

对于超前进位加法器，对于每一位的计算结果，都不依赖于低位的运算，而是根据低位的输入直接求得该位的进位，因此，提高了运算速度，但是也占用了更多的资源。

设计文件

library ieee;
use ieee.std_logic_1164.all;
entity cla_adder is
   port (inp1,inp2 : in std_logic_vector(3 downto 0);
           cin : in std_logic;
           s : out std_logic_vector(3 downto 0);
           outp : out std_logic);
end entity;
architecture behavior of cla_adder is
   signal c : std_logic_vector(4 downto 0);
   signal p,g : std_logic_vector(3 downto 0);
begin
   u1:for i in 0 to 3 generate
       p(i) <= inp1(i) xor inp2(i);
       g(i) <= inp1(i) and inp2(i);
       s(i) <= p(i) xor c(i);
   end generate;
   c(0) <= cin;
   c(1) <= (cin and p(0)) or g(0);
   c(2) <= (cin and p(0) and p(1)) or
               (g(0) and p(1)) or
               g(1);
   c(3) <= (cin and p(0) and p(1) and p(2)) or
               (g(0) and p(1) and p(2)) or
               (g(0) and p(1) and p(2)) or
               g(2);
   c(4) <= (cin and p(0) and p(1) and p(2) and p(3)) or
               (g(0) and p(1) and p(2) and p(3)) or
               (g(0) and p(1) and p(2) and p(3)) or
               (g(2) and p(3)) or
               g(3);
   outp <= c(4);
end architecture;

测试文件

library ieee;
use ieee.std_logic_1164.all;
entity tb_cla_adder is

end entity;
architecture behavior of tb_cla_adder is
   component cla_adder is
   port (inp1,inp2 : in std_logic_vector(3 downto 0);
           cin : in std_logic;
           s : out std_logic_vector(3 downto 0);
           outp : out std_logic);
   end component;
   signal inp1,inp2,s : std_logic_vector(3 downto 0);
   signal cin,outp : std_logic;
begin
   dut : cla_adder
   port map(inp1,inp2,cin,s,outp);
   process
   begin
       inp1 <= "0010";
       inp2 <= "1101";
       cin <='0';
       wait for 20ns;
       cin <= '1';
       wait for 20ns;
       inp1 <= "0110";
       inp2 <= "0101";
       cin <='0';
       wait for 20ns;
       cin <= '1';
       wait for 20ns;
   end process;
end architecture;