实验四ＦＰＧＡ使用Verilog HDL设计电机运动控制程序

实验目的

1.掌握使用GPIO控制直流电机的原理。

2.掌握使用Verilog HDL设计电机运动控制程序的方法。

实验要求

采用Verilog HDL语言设计直流电机运动控制程序，实现直流电机的运动控制，并通过数码管显示当前输出的PWM波的占空比。通过按键或拔位开关可改变电机的转速及转向。

实验过程

1.模块代码如下：

module exp4(input clk,input rst,input [3:0] speed,//档位input dir,//方向output reg out, //PWM波output wire DIR, //方向控制output reg [6:0] print, //数码管输出output reg [7:0] select, //位选//使能output reg CS,output reg RD,output reg WE,output reg [3:0] A1, output reg [4:0] A2,inout wire [7:0] data );reg [31:0] counts; //分频
reg [31:0] h = 1000; //占空比计数//数码管
reg [20:0] n;
reg [1:0] second;//初始化
assign DIR = dir;reg [7:0] D;
assign data = D;    parameter max = 10000;always @(posedge clk)beginif(!rst)begin CS <= 1;D <= 0;end    else beginCS <= 0; D <= 8'b00000001;endendalways@(posedge clk)begincase(speed)4'b0000:beginh <= 0;end4'b0001:beginh <= 1000;end4'b0010:beginh <= 2000;end4'b0011:beginh <= 3000;end4'b0100:beginh <= 4000;end4'b0101:beginh <= 5000;end4'b0110:beginh <= 6000;end4'b0111:beginh <= 7000;end4'b1000:beginh <= 8000;end4'b1001:beginh <= 9000;enddefault:beginh <= 10000;endendcaseendalways@(posedge clk)beginif(counts <= max)counts <= counts + 1;elsecounts <= 0;out <= (counts < h) ? 1 : 0;end
//十进制
always@(h)begincase(h/100)8'd100: n <= 21'b0110000_1111110_1111110;8'd90: n <= 21'b0000000_1111011_1111110;8'd80: n <= 21'b0000000_1111111_1111110;8'd70: n <= 21'b0000000_1110000_1111110;8'd60: n<= 21'b0000000_1011111_1111110;8'd50: n <= 21'b0000000_1011011_1111110;8'd40: n <= 21'b0000000_0110011_1111110;8'd30: n <= 21'b0000000_1111001_1111110;8'd20: n <= 21'b0000000_1101101_1111110;8'd10: n <= 21'b0000000_0110000_1111110;default: n <= 0;endcaseend
//位选
always@(posedge clk)beginif (second < 2)second <= second + 1;elsesecond <= 0;case (second)0:beginselect <= 8'b11111110;print <= n[6:0];end1:beginselect <= 8'b11111101;print <= n[13:7];end2:beginselect <= 8'b11111011;print <= n[20:14];enddefault:beginselect <= 0;print <= 0;endendcaseend
endmodule

2.仿真代码如下：

`timescale 1ns / 1psmodule exp4simulation;reg clk;always #10 clk<=~clk;reg rst;reg [3:0] speed;reg dir;wire out;wire DIR;wire [6:0] print;wire [7:0] select;wire CS;wire RD;wire WE;wire [3:0] A1;wire [4:0] A2;wire [7:0] data;exp4 expt(.clk(clk),.rst(rst),.speed(speed),.dir(dir),.out(out),.DIR(DIR),.print(print),.select(select),.CS(CS),.RD(RD),.WE(WE),.A1(A1),.A2(A2),.data(data));initial beginclk = 0;rst = 1;speed = 4'b0011;dir = 0;speed=4'b0101;#400000speed=4'b1000;#400000$stop;end
endmodule

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