zynq PS端 GPIO

记录一下PS端 GPIO

1. GPIO 简介

ZYNQ PS 中包含一组丰富的外设，用于和外部设备进行通信。ZYNQ 的 IO 包括对外连接的 GPIO 和内部 PS 与 PL 通信的 AXIO。其中对外的 GPIO 又分为两种：MIO 和 EMIO。

MIO 和 EMIO 只是 GPIO 信号的两种接口，MIO 直连到PS，EMIO 则是 PS 扩展到 PL，从 PL 接出的 I/O。EMIO 依然属于 PS，只是连接到了 PL，再从 PL 输出信号。所以 MIO 不需要管脚约束，而 EMIO 需要管脚约束。

MIO 是 I/O 外设连接的基础，软件程序将 I/O 信号路由到 MIO 引脚。由于MIO 引脚数量有限，I/O 外围信号也可以通过 EMIO 接口路由到 PL(包括 PL 设备引脚)，用于访问更多的设备引脚(PL引脚)和允许 I/O 外设控制器接口到 PL中的用户逻辑，如下图所示。

I/O控制器信号的 I/O 复用是不同的，也就是说，一些 IOP （ I/O Peripheral）信号仅在 MIO 接口上可用，如 USB 外设信号；一些信号在 MIO 或 EMIO 接口上可用，如 UART 信号；而一些接口信号只能在 EMIO 接口上访问，如 UART的 Modem signals 接口信号。 I/O 复用如下图所示。

2. GPIO 通道

INT_MASK	This register is read-only and shows which bits are currently masked and which are un-masked/enabled. 这个寄存器是只读的，并显示哪些位当前被屏蔽，哪些位未被屏蔽/启用。
INT_EN	Writing a 1 to any bit of this register enables/unmasks that signal for interrupts. Reading from this register returns an unpredictable value. 将1写入此寄存器的任意位，可启用/揭示中断信号。从这个寄存器中读取会返回一个不可预测的值。
INT_DIS	Writing a 1 to any bit of this register masks that signal for interrupts. Reading from this register returns an unpredictable value. 对这个寄存器的任意一点写入1都会屏蔽中断的信号。从这个寄存器中读取会返回一个不可预测的值。
INT_STAT	This registers shows if an interrupt event has occurred or not. Writing a 1 to a bit in this register clears the interrupt status for that bit. Writing a 0 to a bit in this register is ignored. 此寄存器显示是否发生了中断事件。在这个寄存器中写入一个1到一个位可以清除该位的中断状态。在此寄存器中写入0到某个位将被忽略。
INT_TYPE	This register controls whether the interrupt is edge sensitive or level sensitive. 此寄存器控制中断是对边缘触发还是对电平触发。
INT_POLARITY	This register controls whether the interrupt is active-Low or active High (or falling-edge sensitive or rising-edge sensitive). 此寄存器控制中断是低电平还是高电平（或下降缘触发或上升缘触发）。
INT_ON_ANY	If INT_TYPE is set to edge sensitive, then this register enables an interrupt event on both rising and falling edges. This register is ignored if INT_TYPE is set to level sensitive. 如果INT_TYPE被设置为边缘触发，那么将在上升和下降边缘启用中断事件。如果将INT_TYPE设置为电平触发，则将忽略此寄存器。
DATA_RO	This register enables software to observe the value on the device pin. If the GPIO signal is configured as an output, then this would normally reflect the value being driven on the output. Writes to this register are ignored. *Note:* If the MIO is not configured to enable this pin as a GPIO pin, then DATA_RO is unpredictable because software cannot observe values on non-GPIO pins through the GPIO registers. 此寄存器使软件能够观察设备引脚上的值。如果GPIO信号被配置为一个输出，那么这通常会反映在输出上被驱动的值。写入此寄存器将被忽略。注意：如果MIO没有配置为启用此引脚作为GPIO引脚，那么DATA_RO是不可预测的，因为软件无法通过GPIO寄存器观察非GPIO引脚上的值。
DATA	This register controls the value to be output when the GPIO signal is configured as an output. All 32 bits of this register are written at one time. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the current value on the device pin. 此寄存器控制当GPIO信号配置为输出时要输出的值。这个寄存器的所有32位都是一次写入的。从此寄存器读取将返回先前写入DATA或MASK_DATA_{LSW，MSW}的值；它不返回设备引脚上的当前值。
MASK_DATA_LSW	This register enables more selective changes to the desired output value. Any combination of up to 16 bits can be written. Those bits that are not written are unchanged and hold their previous value. Reading from this register returns the previous value written to either DATA or MASK_DATA_{LSW,MSW}; it does not return the current value on the device pin. This register avoids the need for a read-modify-write sequence for unchanged bits. 此寄存器允许对所需的输出值进行更多选择性的更改。最多16位的任何组合。那些未写入的位保持不变，并保持它们以前的值。从此寄存器读取将返回先前写入DATA或MASK_DATA_{LSW，MSW}的值；它不返回设备引脚上的当前值。这个寄存器避免了对不变的位：读-修改-写。
MASK_DATA_MSW	This register is the same as MASK_DATA_LSW, except it controls the upper16 bits of the bank. 这个寄存器与MASK_DATA_LSW相同，只是它控制了bank的上16位。
DIRM	Direction Mode. This controls whether the I/O pin is acting as an input or an output. Since the input logic is always enabled, this effectively enables/disables the output driver. When DIRM[x]==0 , the output driver is disabled. 方向模式。它控制输入/输出引脚是作为输入还是作为输出。由于输入逻辑总是启用的，因此这可以有效地启用/禁用输出驱动程序。当DIRM[x]==0时，输出驱动程序被禁用。
OEN	Output Enable. When the I/O is configured as an output, this controls whether the output is enabled or not. When the output is disabled, the pin is 3-stated. When OEN[x]==0 , the output driver is disabled. *Note:* If MIO TRI_ENABLE is set to 1 , enabling 3-state and disabling the driver, then OEN is ignored and the output is 3-stated. 输出启用。当I/O配置为输出时，它控制是否启用输出。当输出被禁用时，引脚是三态。当OEN[x]==0时，输出驱动程序被禁用。注意：如果MIO TRI_ENABLE设置为1，启用三态并禁用驱动程序，则OEN将被忽略，输出为三态。