1. Rule 90

module top_module(input clk,input load,input [511:0] data,output [511:0] q ); always@(posedge clk)beginif(load)q<=data;elsebeginq<={1'b0,q[511:1]}^{q[510:0],1'b0}; //左邻居矩阵^右邻居矩阵endendendmodule

2. Rule110

module top_module(input clk,input load,input [511:0] data,output [511:0] q
); always@(posedge clk)beginif(load)q<=data;elsebeginq <= (~{1'b0,q[511:1]} & q) | (q & ~{q[510:0],1'b0}) | {~{1'b0,q[511:1]} & {q[510:0],1'b0}} | {~q & {q[510:0],1'b0}};endendendmodule

3.Conway

module top_module(input clk,input load,input [255:0] data,output [255:0] q );reg [3:0] count;integer i;always @(posedge clk)beginif(load)beginq <= data;endelse beginfor(i=0;i<256;i++)beginif(i == 0)begincount = q[255] + q[240] + q[241] + q[15] + q[1] + q[31] + q[16] + q[17];endelse if(i == 15)begincount = q[254] + q[255] + q[240] + q[14] + q[0] + q[30] + q[31] + q[16];endelse if(i == 240)begincount = q[239] + q[224] + q[225] + q[255] + q[241] + q[15] + q[0] + q[1];endelse if(i == 255)begincount = q[238] + q[239] + q[224] + q[254] + q[240] + q[15] + q[0] + q[14];endelse if( i>0 && i<15)begincount = q[239+i]+q[240+i]+q[241+i]+q[i-1]+q[i+1]+q[i+15]+q[i+16]+q[i+17];endelse if(i>240 && i<255)begincount = q[i-17]+q[i-16]+q[i-15]+q[i-1]+q[i+1]+q[i-239]+q[i-240]+q[i-241];endelse if( i%16 == 0)begincount = q[i-1]+q[i-16]+q[i-15]+q[i+15]+q[i+1]+q[i+31]+q[i+16]+q[i+17];endelse if(i % 16 == 15)begincount = q[i-17]+q[i-16]+q[i-31]+q[i-1]+q[i-15]+q[i+15]+q[i+16]+q[i+1];endelse begincount = q[i-17]+q[i-16]+q[i-15]+q[i-1]+q[i+1]+q[i+15]+q[i+16]+q[i+17];endcase(count)4'd2:q[i] <= q[i];4'd3:q[i] <= 1'b1;default:q[i] <= 1'b0;endcaseendendendendmodule

参考资料：

HDLBits答案(13)_Verilog移位寄存器附加题_题目描述1:各单元的下一状态是此时当前单元相邻两位的异或。 在这个电路中,创建一-CSDN博客