本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益

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题目链接：Sim/circuit1 - HDLBits

module top_module (input a,input b,output q );//assign q = a & b ; // Fix meendmodule

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题目链接：Sim/circuit2 - HDLBits

module top_module (input a,input b,input c,input d,output q );//assign q = (a + b + c + d == 0 | a + b + c + d == 2 | a + b + c + d == 4); endmodule

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题目链接：Sim/circuit3 - HDLBits

module top_module (input a,input b,input c,input d,output q );//assign q = (b & d) | (b & c) | (a & d) | (a & c);endmodule

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题目链接：Sim/circuit4 - HDLBits

module top_module (input a,input b,input c,input d,output q );//assign q = b | c;endmodule

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题目链接：Sim/circuit5 - HDLBits

module top_module (input [3:0] a,input [3:0] b,input [3:0] c,input [3:0] d,input [3:0] e,output [3:0] q 
);always @(*) begincase (c)0 : q = b ; 1 : q = e ; 2 : q = a ; 3 : q = d ; default : q = 4'hf ;endcaseendendmodule

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题目链接：Sim/circuit6 - HDLBits

module top_module (input [2:0] a,output reg [15:0] q ); always@(*)begincase(a)0 : q = 16'h1232;1 : q = 16'haee0;2 : q = 16'h27d4;3 : q = 16'h5a0e;4 : q = 16'h2066;5 : q = 16'h64ce;6 : q = 16'hc526;7 : q = 16'h2f19;endcaseendendmodule

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题目链接：Sim/circuit7 - HDLBits

module top_module (input clk,input a,output q 
);always @(posedge clk) beginq <= ~a ; endendmodule

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题目链接：Sim/circuit8 - HDLBits

module top_module (input clock,input a,output p,output q );always @(*) beginif(clock) p = a;    endalways @(negedge clock) beginq <= p;endendmodule

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题目链接：Sim/circuit9 - HDLBits

module top_module (input clk,input a,output [3:0] q 
);always @(posedge clk) beginif (a) q <= 4 ; else q <= q == 6 ? 0 : q + 1 ; endendmodule

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题目链接：Sim/circuit10 - HDLBits

module top_module (input clk,input a,input b,output q,output state  
);always @(posedge clk) beginif (a == b) state <= a ; else state <= state ; endassign q = (a == b) ? state : ~state ;endmodule