spartan6不能直接把时钟连到IO上

1、问题的提出：spartan6中不允许时钟信号直接连到IO口上面？

2、解决办法：

ODDR2的使用

ODDR2Primitive: Double Data Rate Output D Flip-Flop with Optional Data Alignment, Clock Enable and Programmable Synchronous or Asynchronous Set/Reset

 

The ODDR2 is an output double data rate (DDR) register useful in producing double data-rate signals exiting the FPGA. The ODDR2 requires two clocks to be connected to the component, C0 and C1, so that data is provided at the positive edge of both C0 and C1 clocks. The ODDR2 features an active high clock enable port, CE, which may be used to suspend the operation of the registers and both set and reset ports that may be configured to be synchronous or asynchronous to the respective clocks. The ODDR2 has an optional alignment feature, which allows data to be captured by a single clock yet clocked out by two clocks.

Usage

The ODDR2 currently must be instantiated in order to be incorporated into the design. In order to change the default behavior of the ODDR2, attributes may be modified via the generic map (VHDL) or named parameter value assignment (Verilog) as a part of the instantiated component. The ODDR2 may be either connected directly to a top-level output port in the design where an appropriate output buffer can be inferred or to an instantiated OBUF, IOBUF, OBUFDS, OBUFTDS or IOBUFDS. All inputs and outputs of this component should either be connected or properly tied off.

Available Attributes

DDR_ALIGNMENT – Specifies how the data will be captured on the D0 and D1 ports. When set to "NONE", the data on the D0 port will be aligned with the positive edge of the C0 clock and the data on the D1 port will be aligned with the positive edge of the C1 clock. When set to "C0", the data on both D0 and D1 ports are aligned to the positive edge of the C0 clock and when set to "C1", the data on the D0 and D1 ports are aligned to the positive edge of the C1 clock. The output data Q is always presented on the positive edge of both clocks.

INIT – Specifies the initial value upon power-up or the assertion of GSR for the Q port. This attribute may be set to 1 or 0.

SRTYPE – When set to "SYNC", the reset, R, and set, S, ports are synchronous to the associated clock inputs. When set to "ASYNC", the set and reset ports are asynchronous to the clock.

VHDL Instantiation Templatede style="color: rgb(69, 69, 69); line-height: 21px;" >
-- ODDR2: Output Double Data Rate Input Register with
-- Set, Reset and Clock Enable. Spartan-3E
-- Xilinx HDL Libraries Guide version 7.1i

ODDR2_inst : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- Sets output alignment 
-- to "NONE", "C0" or "C1"
INIT => '0', -- Sets initial state of the Q0 
-- output to ‘0’ or ‘1’
SRTYPE =>= "SYNC") -- Specifies "SYNC" or "ASYNC" 
-- set/reset
port map (
Q => Q, -- 1-bit DDR output data
C0 => C0, -- 1-bit clock input
C1 => C1, -- 1-bit clock input
CE => CE, -- 1-bit clock enable input
D0 => D0, -- 1-bit data input (associated with C1)
D1 => D1, -- 1-bit data input (associated with C1)
R => R, -- 1-bit reset input
S => S -- 1-bit set input
);


-- End of ODDR2_inst instantiation 
de>Verilog Instantiation Templatede style="color: rgb(69, 69, 69); line-height: 21px;" >
// ODDR2: Output Double Data Rate Input Register with
// Set, Reset and Clock Enable. Spartan-3E
// Xilinx HDL Libraries Guide version 7.1i

ODDR2 #(
// The following parameters specify the behavior
// of the component.
.DDR_ALIGNMENT("NONE"), // Sets output alignment 
// to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q 
// output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" 
// set/reset
ODDR2_inst (
.Q(Q), // 1-bit DDR output data
.C0(C0), // 1-bit clock input
.C1(C1), // 1-bit clock input
.CE(CE), // 1-bit clock enable input
.D0(D0), // 1-bit data input (associated with C0)
.D1(D1), // 1-bit data input (associated with C1)
.R(R), // 1-bit reset input
.S(S) // 1-bit set input
);


// End of ODDR2_inst instantiation 
de>For More Information

Consult the Spartan-3E Data Sheets.