状态机在VHDL中的实现

1、Moore状态机的VHDL描述
输出仅取决于所处的状态

LIBRARY IEEE;    --库、程序包的说明调用
USE IEEE.STD_LOGIC_1164.ALL;ENTITY Moore IS 
PORT
(RESET,CLOCK,DIN : IN STD_LOGIC;DOUT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
);
END;ARCHITECTURE Mooremachine OF Moore IS 
TYPE State_type IS (S0,S1,S2,S3);--定义State_type为枚举型数据类型
SIGNAL State : State_type;
BEGIN
Change_State : PROCESS(RESET,CLOCK)  --时序逻辑进程
BEGINIF RESET = '1' EHRNState <= S0;ELSEIF RISING_EDGE(CLOCK)THENCASE State IS WHEN S0 => IF DIN='1' THEN State<=S1;END IF;WHEN S1 => IF DIN='1' THEN State<=S2;END IF;WHEN S2 => IF DIN='1' THEN