专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

`timescale 1ns/1nsmodule game_count(input rst_n, //异位复位信号，低电平有效input clk, 	//时钟信号input [9:0]money,input set,input boost,output reg[9:0]remain,output reg yellow,output reg red);always @ (posedge clk or negedge rst_n) begin if (~rst_n) remain <= 0 ;  else if (boost) remain <= set ? remain + money : remain < 2 ? remain : remain - 2 ; else remain <= set ? remain + money : remain < 1 ? remain : remain - 1 ; endalways @ (posedge clk or negedge rst_n) begin if (~rst_n) begin yellow <= 0 ; red <= 0 ; endelse begin yellow <= remain && remain < 10 ; red <= boost ? remain < 2 : remain < 1 ;endend
endmodule