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DM9161A
DM9161A是一款高性能的以太网物理层收发器（PHY），它支持MII（介质独立接口）和RMII（减少MII接口）两种接口标准，并且具有低功耗、低成本、高集成度等特点。在网络通信中，PHY负责将数字信号转换为模拟信号，然后通过物理介质（如双绞线）传输到远端设备的PHY，再由远端PHY将模拟信号转换为数字信号，最终交给网络协议栈进行处理。因此，PHY是网络通信中不可或缺的一部分。
描述
DM9161A是一个物理层，单芯片，低功耗收发器，用于100BASE-TX和10BASE-T操作。在媒体端，它为100BASE-TX快速以太网提供非屏蔽双绞线5电缆(UTP5)的直接接口，或为10BASE-T以太网提供UTP5/UTP3电缆的直接接口。DM9161A通过媒体独立接口(MII)连接到媒体访问控制(MAC)层，确保不同厂商的高互操作性。
DM9161a采用低功耗、高性能的先进CMOS工艺。它包含了IEEE802.3u定义的100BASE-TX的全部物理层功能，包括物理编码子层(PCS)、物理介质附件(PMA)、双绞线物理介质依赖子层(TP-PMD)、10BASE-TX编/解码器(ENC/DEC)和双绞线媒体访问单元(TPMAU)。DM9161A提供了强大的自动协商功能支持，利用自动媒体速度和协议选择。此外，由于内置整形滤波器，DM9161A不需要外部滤波器在100BASE-TX或10BASE-T以太网操作中将信号传输到媒体。
框图
引脚图
引脚说明
I:输入，O:输出，Ll:上电/复位锁存输入，Z:三态输出、U:高拉、D:低拉。
| Pin No. | Pin Name | I/O | Description |
| 16 | TXER/TXD [4] | I | Transmit Error/The Fifth TXD Data Bit In 100Mbps mode, when the signal indicates active high and TXEN is active, the HALT symbol substitutes the actual data nibble. In 10Mbps, the input is ignored In bypass mode (bypass BP4B5B), TXER becomes the TXD [4] pin, the fifth TXD data bit of the 5B symbol |
| 20,19,18,17 | TXD [0:3] | I | Transmit Data 4-bit nibble data inputs (synchronous to the TXCLK) when in 10/100Mbps nibble mode. In 10Mbps GPSI (7-Wired) mode, the TXD [0] pin is used as the serial data input pin, and TXD [1:3] are ignored. |
| 21 | TXEN | I | Transmit Enable Active high indicates the presence of valid nibble data on the TXD [0:3] for both 100Mbps and 10Mbps nibble modes. In 10Mbps GPSI (7-Wired) mode, active high indicates the presence of valid 10Mbps data on TXD [0]. |
| 22 | TXCLK/ ISOLATE | O, Z, LI (D) | Transmit Clock The transmitting clock provides the timing reference for the transfer of the TXEN, TXD, and TXER. TXCLK is provided by the PHY 25MHz in 100Mbps nibble mode, 2.5MHz in 10Mbps nibble mode, 10MHz in 10Mbps GPSI (7-Wired) mode ISOLATE Setting: (When power up reset, latch input) 0: Reg 0.10 will be initialized to “0”. (Ref.to 8.1 Basic Control Register) 1: Reg 0.10 will be initialized to “1”. |
| 24 | MDC | I | Management Data Clock Synchronous clock for the MDIO management data. This clock is provided by management entity, and it is up to 12.5MHz |
| 25 | MDIO | I/O | Management Data I/O Bi-directional management data which may be provided by the station management entity or the PHY |
| 29,28,27,26 | RXD[0:3] /PHYAD[0:3] | O, Z, LI (D) | Receive Data Output 4-bit nibble data outputs (synchronous to RXCLK) when in 10/100Mbps MII mode In 10Mbps GPSI (7-Wired) mode, the RXD [0] pin is used as the serial data output pin, and the RXD [1:3] are ignored PHY address [0:3] (power up reset latch input) PHY address sensing input pins |
| 32 | MDINTR | IO, LI (D) | Status Interrupt Output: Whenever there is a status change (link, speed, duplex depend on interrupt register [21] ) The interrupt output assert low when pull up. Asserted high when pull down. |
| 34 | RXCLK /10BTSER | O, Z, LI (U) | Receive Clock The received clock provides the timing reference for the transfer of the RXDV, RXD, and RXER. RXCLK is provided by PHY. The PHY may recover the RXCLK reference from the received data or it may derive the RXCLK reference from a nominal clock 25MHz in 100Mbps MII mode, 2.5MHz in 10Mbps MII mode, 10MHz in 10Mbps GPSI (7-Wired) mode 10BTSER only support for 10M mode; (power up reset latch input) 0 = GPSI (7-Wired) mode in 10M mode 1 = MII mode in 10M mode |
| 35 | CRS /PHYAD[4] | O, Z, LI (D) | Carrier Sense Detect/ PHYAD[4] Asserted high to indicate the presence of carrier due to receive or transmit activities in half-duplex mode of 10BASE-T or 100BASE-TX. In repeater mode or full-duplex mode, this signal is asserted high to indicate the presence of carrier due to receive activity only This pin is also used as PHYAD [4] (power up reset latch input) PHY address sensing input pin |
| 36 | COL /RMII | O, Z, LI (D) | Collision Detection Asserted high to indicate the detection of the collision conditions in half-duplex mode of 10Mbps and 100Mbps. In full-duplex mode, this signal is always logical 0 Reduced MII enable: This pin is also used to select Normal MII or Reduced MII. (power up reset latch input) 0= Normal MII (default) 1= Reduced MII This pin is always pulled low except used as reduced MII |
| 37 | RXDV /TESTMODE | O, Z, LI (D) | Receive Data Valid Asserted high to indicate that the valid data is presented on the RXD [0:3] Test mode control pin (power up reset latch input) 0 = normal operation (default) 1 = enable test mode |
| 38 | RXER/RXD[4] /RPTR | O, Z, LI (D) | Receive Data Error/The Fifth RXD Data Bit of the 5B Symbol Asserted high to indicate that an invalid symbol has been detected In decoder bypass mode (bypass BP4B5B), RXER becomes RXD [4], the fifth RXD data bit of the 5B symbol This pin is also used to select Repeater or Node mode. (power up reset latch input) 0 = Node Mode (default) 1 = Repeater Mode |
| 31 | LEDMODE | I | LED MODE Select Reference LED function description 0: support Dual-LED 1: Normal LED |
| 40 | RESET# | I | Reset Active low input that initializes the DM9161A |
5.2 Media Interface, 4 pins
| Pin No. | Pin Name | I/O | Description |
| 3,4 | RX+ RX | I | Differential Receive Pair Differential data is received from the media |
| 7,8 | TX+ TX | O | Differential Transmit Pair/PECL Transmit Pair Differential data is transmitted to the media in TP mode |
5.3 LED Interface, 3 pins
| Pin No. | Pin Name | I/O | Description |
| 11 | LED0 /OP0 | O, LI (U) | LED Driver output 0 OP0: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161A according to the Table A. The value is latched into the DM9161A registers at power-up/reset |
| 12 | LED1 /OP1 | O, LI (U) | LED Driver output 1 OP1: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161A according to the Table A. The value is latched into the DM9161A registers at power-up/reset |
| 13 | LED2 /OP2 | O, LI (U) | LED Driver output 2 OP2: (power up reset latch input) This pin is used to control the forced or advertised operating mode of the DM9161A according to the Table A. The value is latched into the DM9161A registers at power-up/reset |
5.4 Mode, 3 pins
| Pin No. | Pin Name | I/O | Description |
| 10 | PWRDWN | I | Power Down Control Asserted high to force the DM9161A into power down mode. When in power down mode, most of the DM9161A circuit block’s power is turned off, only the MII management interface (MDC, MDIO) logic is available (the PHY should respond to management transactions and should not generate spurious signals on the MII)). To leave power down mode, the DM9161A needs the hardware or software reset with the PWRDWN pin low |
| 14 | CABLESTS /LINKSTS | O, LI (D) | Cable Status or Link Status This pin is used to indicate the status of the cable connection when power up reset latch low (Default) 0 = Without cable connection 1 = With cable connection This pin is used to indicate the status of the Link connection when power up reset latch high 0 = With link 1 = Without link |
| 39 | DISMDIX | I (D) | HP Auto-MDIX Control 1: Disable auto mode 0: Enable HP Auto-MDIX mode |
5.5 Bias and Clock, 4 pins
| Pin No. | Pin Name | I/O | Description |
| 47 | BGRESG | P | Bandgap Ground |
| 48 | BGRES | O | Bandgap Voltage Reference Resistor 6.8K ohm +/- 1% |
| 42 | XT2 | I/O | Crystal Output; REF_CLK input for RMII mode |
| 43 | XT1 | I | Crystal Input |
5.6 Power, 12 pins
| Pin No. | Pin Name | I/O | Description |
| 1,2 | AVDDR | P | Analog Receive Power output |
| 9 | AVDDT | P | Analog Transmit Power output |
| 5 | AGND | P | Analog Receive Ground |
| 6 | AGND | P | Analog Transmit Ground |
| 46 | AGND | P | Analog Substrate Ground |
| 23,30,41 | DVDD | P | Digital Power |
| 15,33,44 | DGND | P | Digital Ground |
5.7 Table A (Media Type Selection)
| OP2 | OP1 | OP0 | Function |
| 0 | 0 | 0 | Dual Speed 100/10 HDX |
| 0 | 0 | 1 | Reserved |
| 0 | 1 | 0 | Reserved |
| 0 | 1 | 1 | Manually Select 10TX HDX |
| 1 | 0 | 0 | Manually Select 10TX FDX |
| 1 | 0 | 1 | Manually Select 100TX HDX |
| 1 | 1 | 0 | Manually Select 100TX FDX |
| 1 | 1 | 1 | Auto-negotiation Enables All Capabilities |
5.8 Pin Maps of Normal MII, Reduced MII, and 10Base-T GPSI (7-Wired) Mode
| Normal MII Mode | Reduced MII Mode | 10Base-T GPSI (7-Wired) Mode |
| TXD [0:1] | TXD [0:1] | TXD [0] ; TXD [1] = NC |
| TXD [2:3] | NC | NC |
| TXEN | TXEN | TXEN |
| TXER/TXD [4] | NC | NC |
| TXCLK | NC | TXCLK |
| RXD [0:1] | RXD [0:1] | RXD [0] ; RXD [1] = NC |
| RXD[2:3] | NC | NC |
| RXER/RXD[4]/RPTR/NODE | RPTR/NODE | RPTR/NODE |
| RXDV | CRS DV | NC |
| RXCLK | NC | RXCLK |
| COL | NC | COL |
| CRS (PHYADR [2:4]) (BP4B5B) | NC | CRS |
| MDC | MDC | MDC |
| MDIO | MDIO | MDIO |
| RESET# | RESET# | RESET# |
| XT1 (25 MHz) | XT2 (REF_CLK 50MHz) | XT1 (25 MHz) |
