实验要求：
采用 3 个开关以二进制形式设定分频系数（0-7），实现对已知信号的分频。

实现代码（VHDL）：

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use ieee.std_logic_unsigned.all ;entity Division isport(sw : in std_logic_vector(2 downto 0) ;clk : in std_logic ;ld : buffer std_logic) ;
end Division ;architecture Delay of Division issignal num : integer := 0 ;		-- the times of rising edge ;signal num1 : integer := 0 ;	-- the times of falling edge ;signal result : std_logic := '0' ;		-- when clk is rising ;signal result1 : std_logic := '0' ;		-- when clk is falling ;
beginprocess(sw, clk)variable n : integer := 0 ;variable n1 : integer := 0 ;beginif rising_edge(clk) thennum <= num + 1 ;if (sw = "011" or sw = "101" or sw = "111") thenif (sw = "011") thenn := 3 ;elsif (sw = "101") thenn := 5 ;elsif (sw = "111") thenn := 7 ;end if ;if (n = 3 and (num = 2 or ((num-2) rem n = 0)) ) thenresult <= Not result ;elsif (n = 5 and (num = 3 or ((num-3) rem n = 0)) ) thenresult <= Not result ;elsif (n = 7 and (num = 4 or ((num-4) rem n = 0)) ) thenresult <= Not result ;end if ;end if ;elsif falling_edge(clk) thennum1 <= num1 + 1 ;if (sw = "010" or sw = "100" or sw = "110") thenif (sw = "010") thenn1 := 2 ;elsif (sw = "100") thenn1 := 4 ;elsif (sw = "110") thenn1 := 6 ;end if ;if (num1 = (n1/2) or ((num1 - (n1/2)) rem n1 = 0)) thenresult1 <= Not result1 ;elsif (num1 rem n1 = 0) thenresult1 <= Not result1 ;end if ;elsif (sw = "011" or sw = "101" or sw = "111") thenif (sw = "011") thenn1 := 3 ;elsif (sw = "101") thenn1 := 5 ;elsif (sw = "111") thenn1 := 7 ;end if ;if (num1 rem n1 = 0) thenresult1 <= Not result1 ;end if ;end if ;end if ;ld <= result xor result1 ;end process ;
end Delay ;