专栏前言

本专栏的内容主要是记录本人学习Verilog过程中的一些知识点，刷题网站用的是牛客网

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`timescale 1ns/1ns
module edge_detect(input clk,input rst_n,input a,output reg rise,output reg down
);reg a_tem ; always @ (posedge clk or negedge rst_n) beginif (!rst_n) a_tem <= 1'b0 ; else a_tem <= a ; endalways @ (posedge clk or negedge rst_n) begin if (!rst_n) beginrise <= 1'b0 ;down <= 1'b0 ; endelse if (!a_tem && a) beginrise <= 1'b1 ; down <= 1'b0 ; endelse if (a_tem && !a) beginrise <= 1'b0 ; down <= 1'b1 ; endelse beginrise <= 1'b0 ;down <= 1'b0 ; endend
endmodule