杂谈：DC对Verilog和SystemVerilog语言的支持

DC对Verilog和SystemVerilog语言的支持

设计语言用哪种？
Design Compiler对二者的支持
简单的fsm电路测试
测试结果对比
写在最后

设计语言用哪种？

直接抛出结论：先有电路，后为描述。
设计端而言，没有语言的高低好坏，只有描述的精准与否。本文的实验结果很好的说明了这一点。

Design Compiler对二者的支持

我们在Design Compiler中读入命令有这样的选项，支持包括v和sv在内的三种主流硬件描述语言。

简单的fsm电路测试

分别给出一个简单的FSM电路的V代码和SV代码。并基于SAED32nm学习用工艺库来做DCT的实现。
代码如下


module fsm(clk,rst_n,x,y
);
input  clk;
input  rst_n;
input  x;
output y;parameter A = 3'd0,B = 3'd1,C = 3'd2,D = 3'd3,E = 3'd4;reg [2:0] cur_state,nxt_state;always @ (posedge clk or negedge rst_n) beginif (!rst_n) begincur_state <= A;endelse begincur_state <= nxt_state;end
endalways @(*) beginif (!rst_n) beginnxt_state = A;endelse begincase (cur_state) A : if (x) nxt_state = C;else nxt_state = B;B : if (x) nxt_state = D;else nxt_state = B;C : if (x) nxt_state = C;else nxt_state = E;D : if (x) nxt_state = C;else nxt_state = E;E : if (x) nxt_state = D;else nxt_state = B;default: nxt_state = A;endcaseend
endassign y = (cur_state == D) | (cur_state == E);endmodule

module fsm(clk,rst_n,x,y
);
input logic clk;
input logic rst_n;
input logic x;
output logic y;typedef enum logic [2:0] {A,B,C,D,E} State;State cur_state,nxt_state;always_ff @ (posedge clk or negedge rst_n) beginif (!rst_n) begincur_state <= A;endelse begincur_state <= nxt_state;end
endalways_comb beginif (!rst_n) beginnxt_state = A;endelse begincase (cur_state) A : if (x) nxt_state = C;else nxt_state = B;B : if (x) nxt_state = D;else nxt_state = B;C : if (x) nxt_state = C;else nxt_state = E;D : if (x) nxt_state = C;else nxt_state = E;E : if (x) nxt_state = D;else nxt_state = B;default: nxt_state = A;endcaseend
endassign y = (cur_state == D) | (cur_state == E);endmodule