python自动例化verilog
使用方法：在gvim页面，使用命令自动例化
:r !AUTO_inst xxx.v

#python
import re
import sysmdl_re = r"\s*module\s*(?P<mname>\w+) *"
port_re= r"\s*(?P<dir>input|output)\s+(?P<typ>wire|reg)?\s*(?P<sign>signed)?\s*(?P<width>\[[\s0-9:]+\])?\s*(?P<name>\w+)\s*(,|;)?"
sig_re = r"\s*(?P<typ>wire|reg)\s*(?P<sign>signed)?\s*(?P<width>\[[\s0-9:]+\])?\s*(?P<name>\w+)\s*(,|;)?"def get_ports(mfile):fm = open(mfile,"r")port_list=[]mname = ""while True:line = fm.readline()if not line:breakelse:res = re.match(mdl_re,line)if res != None:mname = res.group("mname")continueres = re.match(port_re,line)if res != None:sig = {"name":res.group("name"),"dir":res.group("dir"),"typ":res.group("typ"),"sign":res.group("sign"),"width":res.group("width")}port_list.append(sig)print("// instance auto-connetion")if(mname==""):Warning("name of module is not detected!")return -1else:print(f"{mname} u_{mname}(")if(len(port_list)==0)Warning("port in module is not detected!")return -2else:max_slen = max([len(sig["name"]) for sig in port_list])max_width= max_slen+4 if max_slen%4==0 else max_slen + (4-max_slen%4)for i,sig in enumerate(port_list):end_flag = "" if i == (len(port_list)-1) else ","sig_name = sig["name"]print(f"\t.{sig_name:<{max_slen+1}}({sig_name:<{max_slen+1}}){end_flag}")print(f");")return port_listif __name__ == "__main__":get_ports(sys.argv[1])