Clock Verification IP

IP 参数及接口

IP 例化界面

相关函数

start_clock

//产生时钟 
<hierarchy_path>.IF.start_clock

stop_clock

//停止时钟 
<hierarchy_path>.IF.stop_clock

set_initial_value

//设置时钟初始值为 0
<hierarchy_path>IF.set_initial_value(0)
//设置时钟初始值为 1
<hierarchy_path>IF.set_initial_value(1)

set_clk_prd

//设置时钟周期、占空比、抖动是能、抖动范围
<hierarchy_path>IF.set_clk_prd(.user_period(200),.user_duty_cycle(0.3),.user_jitter_on(1),.user_jitter_min_range(0.0),.user_jitter_max_range(0.01));

set_clk_frq

//设置时钟频率、占空比、抖动是能、抖动范围
<hierarchy_path>IF.set_clk_prd(.user_frequency(10000000),.user_duty_cycle(0.3),.user_jitter_on(1),.user_jitter_min_range(0.0),.user_jitter_max_range(0.01));

set_master_mode

//设置 CLK_VIP 模式为 Master
< hierarchy_path>.set_master_mode();

set_passthrough_mode

//设置 CLK_VIP 模式为 passthrough
< hierarchy_path>.set_passthrough_mode();

参考代码

`timescale 1ps / 1ps
`include "clk_monitor.sv"module clk_vip_0_exdes_tb();wire                                                                     clk_out;//Declare monitor for master CLK VIP clk_monitor#(10.0)                                       mst_monitor;//Declare monitor for passthrough CLK VIP clk_monitor#(10.0)                                       passthrough_monitor;initial begin/*******************************************************************************************   *    The hierarchy path of the CLK VIP's interface is passed to the monitor when it is newed*    construct mst_monitor and assign the master clk vip interface to its virtual interface*    construct passthrough_monitor and assign the passthrough clk vip interface to its*    virtual interface*******************************************************************************************/mst_monitor =new("Clk mst_monitor",clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_mst.inst.IF);passthrough_monitor =new("Clk passthrough_monitor",clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.IF);/******************************************************************************************* switch passthrough VIP into runtime master mode*     8.1 start clock-- this will generate the default clk with period(default passthrough clk*         vip period) with no jitter,  duty cycle 50%*     8.2 turn on mst_monitor clk check with expected clk settings*******************************************************************************************/clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.set_master_mode();#1ns;clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.IF.set_initial_value(0);clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.IF.start_clock();passthrough_monitor.enable_clk_check(.expected_period(10.0),.expected_duty_cycle(0.50),.expected_jitter(0.0));#(10.0*10*1ns);/*******************************************************************************************  *     9.1 update clock by calling set_clk_prd with clock period, duty cycle,jitter on/off,*        jitter minmum range, jitter maximum range,if jitter is on,it means*        that the jitter is randomized picked between jitter minmum range and jitter maximum*        range)*     9.2 turn on the monitor check with expected clock period, duty cycle and jitter*******************************************************************************************/clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.IF.set_clk_prd(.user_period(1000),.user_duty_cycle(0.3),.user_jitter_on(1),.user_jitter_min_range(0.0),.user_jitter_max_range(0.01));passthrough_monitor.enable_clk_check(.expected_period(1000),.expected_duty_cycle(0.3),.expected_jitter(0.01));#4000ns;/******************************************************************************************* *   10.1 update clock by calling set_clk_frq with clock frequency, duty cycle,jitter on/off,*        jitter minmum range, jitter maximum range,if jitter is on,it means *        that the jitter is randomized picked between jitter minmum range and jitter maximum*        range)*    10.2 turn on the monitor check with expected clock period, duty cycle and jitter*******************************************************************************************/clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.IF.set_clk_frq(.user_frequency(10000000),.user_duty_cycle(0.7),.user_jitter_on(0),.user_jitter_min_range(0.0),.user_jitter_max_range(0.00));passthrough_monitor.enable_clk_check(.expected_period(100),.expected_duty_cycle(0.7),.expected_jitter(0));#810ns;/*******************************************************************************************  * update clock again with different period and duty cycle*******************************************************************************************/clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.IF.set_clk_prd(.user_period(200),.user_duty_cycle(0.4),.user_jitter_on(1),.user_jitter_min_range(0.0),.user_jitter_max_range(0.02));passthrough_monitor.enable_clk_check(.expected_period(200),.expected_duty_cycle(0.4),.expected_jitter(0.0));#1080ns;/******************************************************************************************* * stop clock and disable passthrough monitor*******************************************************************************************/clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.IF.stop_clock();passthrough_monitor.disable_clk_check();#1;/*******************************************************************************************  * set clk_vip_passthrough back into passthrough mode*******************************************************************************************/clk_vip_0_exdes_tb.DUT.ex_design.clk_vip_passthrough.inst.set_passthrough_mode();#(10*1ns);$display("EXAMPLE TEST DONE : Test Completed Successfully");$finish;endchip DUT(.clk_out(clk_out));endmodule

官方手册：pg291-clk-vip