QEMU源码全解析 —— virtio（9）

接前一篇文章：

上两回讲解了virtio balloon相关类所涉及的realize函数以及大致流程，如下表所示：

	realize函数	parent_dc_realize函数
DeviceClass	virtio_pci_dc_realize
PCIDeviceClass	virtio_pci_realize
VirtioPCIClass	virtio_balloon_pci_realize	pci_qdev_realize

本回对于流程进行深入解析。

综合前文书所讲，当具现化TYPE_VIRTIO_BALLOON的时候，device_set_realized函数中会首先调用DeciceClass->realize即virtio_pci_dc_realize函数。再次贴出该函数源码，在hw/virtio/virtio-pci.c中，如下：

static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp)
{VirtioPCIClass *vpciklass = VIRTIO_PCI_GET_CLASS(qdev);VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev);PCIDevice *pci_dev = &proxy->pci_dev;if (!(proxy->flags & VIRTIO_PCI_FLAG_DISABLE_PCIE) &&virtio_pci_modern(proxy)) {pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;}vpciklass->parent_dc_realize(qdev, errp);
}

virtio_pci_dc_realize函数首先判断virtio PCI代理设备是否具有VIRTIO_PCI_FLAG_DISABLE_PCIE特性，该特性使得virtio PCI代理展现出PCIe的的接口。

然后调用了vpciklass->parent_dc_realize函数，由前文分析可知，该回调函数是pci_qdev_realize()。再次贴出pci_qdev_realize函数源码，在hw/virtio/virtio-pci.c中，如下：

static void pci_qdev_realize(DeviceState *qdev, Error **errp)
{PCIDevice *pci_dev = (PCIDevice *)qdev;PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);ObjectClass *klass = OBJECT_CLASS(pc);Error *local_err = NULL;bool is_default_rom;uint16_t class_id;/** capped by systemd (see: udev-builtin-net_id.c)* as it's the only known user honor it to avoid users* misconfigure QEMU and then wonder why acpi-index doesn't work*/if (pci_dev->acpi_index > ONBOARD_INDEX_MAX) {error_setg(errp, "acpi-index should be less or equal to %u",ONBOARD_INDEX_MAX);return;}/** make sure that acpi-index is unique across all present PCI devices*/if (pci_dev->acpi_index) {GSequence *used_indexes = pci_acpi_index_list();if (g_sequence_lookup(used_indexes,GINT_TO_POINTER(pci_dev->acpi_index),g_cmp_uint32, NULL)) {error_setg(errp, "a PCI device with acpi-index = %" PRIu32" already exist", pci_dev->acpi_index);return;}g_sequence_insert_sorted(used_indexes,GINT_TO_POINTER(pci_dev->acpi_index),g_cmp_uint32, NULL);}if (pci_dev->romsize != -1 && !is_power_of_2(pci_dev->romsize)) {error_setg(errp, "ROM size %u is not a power of two", pci_dev->romsize);return;}/* initialize cap_present for pci_is_express() and pci_config_size(),* Note that hybrid PCIs are not set automatically and need to manage* QEMU_PCI_CAP_EXPRESS manually */if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) &&!object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) {pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;}if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) {pci_dev->cap_present |= QEMU_PCIE_CAP_CXL;}pci_dev = do_pci_register_device(pci_dev,object_get_typename(OBJECT(qdev)),pci_dev->devfn, errp);if (pci_dev == NULL)return;if (pc->realize) {pc->realize(pci_dev, &local_err);if (local_err) {error_propagate(errp, local_err);do_pci_unregister_device(pci_dev);return;}}/** A PCIe Downstream Port that do not have ARI Forwarding enabled must* associate only Device 0 with the device attached to the bus* representing the Link from the Port (PCIe base spec rev 4.0 ver 0.3,* sec 7.3.1).* With ARI, PCI_SLOT() can return non-zero value as the traditional* 5-bit Device Number and 3-bit Function Number fields in its associated* Routing IDs, Requester IDs and Completer IDs are interpreted as a* single 8-bit Function Number. Hence, ignore ARI capable devices.*/if (pci_is_express(pci_dev) &&!pcie_find_capability(pci_dev, PCI_EXT_CAP_ID_ARI) &&pcie_has_upstream_port(pci_dev) &&PCI_SLOT(pci_dev->devfn)) {warn_report("PCI: slot %d is not valid for %s,"" parent device only allows plugging into slot 0.",PCI_SLOT(pci_dev->devfn), pci_dev->name);}if (pci_dev->failover_pair_id) {if (!pci_bus_is_express(pci_get_bus(pci_dev))) {error_setg(errp, "failover primary device must be on ""PCIExpress bus");pci_qdev_unrealize(DEVICE(pci_dev));return;}class_id = pci_get_word(pci_dev->config + PCI_CLASS_DEVICE);if (class_id != PCI_CLASS_NETWORK_ETHERNET) {error_setg(errp, "failover primary device is not an ""Ethernet device");pci_qdev_unrealize(DEVICE(pci_dev));return;}if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)|| (PCI_FUNC(pci_dev->devfn) != 0)) {error_setg(errp, "failover: primary device must be in its own ""PCI slot");pci_qdev_unrealize(DEVICE(pci_dev));return;}qdev->allow_unplug_during_migration = true;}/* rom loading */is_default_rom = false;if (pci_dev->romfile == NULL && pc->romfile != NULL) {pci_dev->romfile = g_strdup(pc->romfile);is_default_rom = true;}pci_add_option_rom(pci_dev, is_default_rom, &local_err);if (local_err) {error_propagate(errp, local_err);pci_qdev_unrealize(DEVICE(pci_dev));return;}pci_set_power(pci_dev, true);pci_dev->msi_trigger = pci_msi_trigger;
}

pci_qdev_realize函数会将virtioPCI代理设备注册到PCI总线上，并调用PCIDeviceClass->realize函数指针所指向的函数，也就是virtio_pci_realize函数。代码片段如下：

    pci_dev = do_pci_register_device(pci_dev,object_get_typename(OBJECT(qdev)),pci_dev->devfn, errp);if (pci_dev == NULL)return;if (pc->realize) {pc->realize(pci_dev, &local_err);if (local_err) {error_propagate(errp, local_err);do_pci_unregister_device(pci_dev);return;}}

virtio_pci_realize函数在hw/virtio/virtio-pci.c中，代码如下：

static void virtio_pci_realize(PCIDevice *pci_dev, Error **errp)
{VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);VirtioPCIClass *k = VIRTIO_PCI_GET_CLASS(pci_dev);bool pcie_port = pci_bus_is_express(pci_get_bus(pci_dev)) &&!pci_bus_is_root(pci_get_bus(pci_dev));if (kvm_enabled() && !kvm_has_many_ioeventfds()) {proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;}/* fd-based ioevents can't be synchronized in record/replay */if (replay_mode != REPLAY_MODE_NONE) {proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD;}/** virtio pci bar layout used by default.* subclasses can re-arrange things if needed.**   region 0   --  virtio legacy io bar*   region 1   --  msi-x bar*   region 2   --  virtio modern io bar (off by default)*   region 4+5 --  virtio modern memory (64bit) bar**/proxy->legacy_io_bar_idx  = 0;proxy->msix_bar_idx       = 1;proxy->modern_io_bar_idx  = 2;proxy->modern_mem_bar_idx = 4;proxy->common.offset = 0x0;proxy->common.size = 0x1000;proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;proxy->isr.offset = 0x1000;proxy->isr.size = 0x1000;proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;proxy->device.offset = 0x2000;proxy->device.size = 0x1000;proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;proxy->notify.offset = 0x3000;proxy->notify.size = virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX;proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;proxy->notify_pio.offset = 0x0;proxy->notify_pio.size = 0x4;proxy->notify_pio.type = VIRTIO_PCI_CAP_NOTIFY_CFG;/* subclasses can enforce modern, so do this unconditionally */memory_region_init(&proxy->modern_bar, OBJECT(proxy), "virtio-pci",/* PCI BAR regions must be powers of 2 */pow2ceil(proxy->notify.offset + proxy->notify.size));if (proxy->disable_legacy == ON_OFF_AUTO_AUTO) {proxy->disable_legacy = pcie_port ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;}if (!virtio_pci_modern(proxy) && !virtio_pci_legacy(proxy)) {error_setg(errp, "device cannot work as neither modern nor legacy mode"" is enabled");error_append_hint(errp, "Set either disable-modern or disable-legacy"" to off\n");return;}if (pcie_port && pci_is_express(pci_dev)) {int pos;uint16_t last_pcie_cap_offset = PCI_CONFIG_SPACE_SIZE;pos = pcie_endpoint_cap_init(pci_dev, 0);assert(pos > 0);pos = pci_add_capability(pci_dev, PCI_CAP_ID_PM, 0,PCI_PM_SIZEOF, errp);if (pos < 0) {return;}pci_dev->exp.pm_cap = pos;/** Indicates that this function complies with revision 1.2 of the* PCI Power Management Interface Specification.*/pci_set_word(pci_dev->config + pos + PCI_PM_PMC, 0x3);if (proxy->flags & VIRTIO_PCI_FLAG_AER) {pcie_aer_init(pci_dev, PCI_ERR_VER, last_pcie_cap_offset,PCI_ERR_SIZEOF, NULL);last_pcie_cap_offset += PCI_ERR_SIZEOF;}if (proxy->flags & VIRTIO_PCI_FLAG_INIT_DEVERR) {/* Init error enabling flags */pcie_cap_deverr_init(pci_dev);}if (proxy->flags & VIRTIO_PCI_FLAG_INIT_LNKCTL) {/* Init Link Control Register */pcie_cap_lnkctl_init(pci_dev);}if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {/* Init Power Management Control Register */pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,PCI_PM_CTRL_STATE_MASK);}if (proxy->flags & VIRTIO_PCI_FLAG_ATS) {pcie_ats_init(pci_dev, last_pcie_cap_offset,proxy->flags & VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED);last_pcie_cap_offset += PCI_EXT_CAP_ATS_SIZEOF;}if (proxy->flags & VIRTIO_PCI_FLAG_INIT_FLR) {/* Set Function Level Reset capability bit */pcie_cap_flr_init(pci_dev);}} else {/** make future invocations of pci_is_express() return false* and pci_config_size() return PCI_CONFIG_SPACE_SIZE.*/pci_dev->cap_present &= ~QEMU_PCI_CAP_EXPRESS;}virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);if (k->realize) {k->realize(proxy, errp);}
}

（1）virtio_pci_realize函数首先初始化virtioPCI代理设备，也就是VirtIOPCIProxy结构。代码片段如下：

    VirtIOPCIProxy *proxy = VIRTIO_PCI(pci_dev);

（2）然后，virtio_pci_realize函数初始化VirtIOPCIProxy设备的多个BAR数据，设置了这些BAR的索引号。代码片段如下：

    /** virtio pci bar layout used by default.* subclasses can re-arrange things if needed.**   region 0   --  virtio legacy io bar*   region 1   --  msi-x bar*   region 2   --  virtio modern io bar (off by default)*   region 4+5 --  virtio modern memory (64bit) bar**/proxy->legacy_io_bar_idx  = 0;proxy->msix_bar_idx       = 1;proxy->modern_io_bar_idx  = 2;proxy->modern_mem_bar_idx = 4;

其中：

legacy I/O地址为0；

msi-x地址为1；

modern IO地址为2；

modern MMIO地址为4。

这里的legacy和modern指的是不同的virtio版本。

（3）virtio_pci_realize函数还初始化了多个VirtIOPCIRegion（VirtIOPCIRegion用来表示virtio设备的配置空间信息），如VirtIOProxy的common、isr、device、notify成员。代码片段如下：

    proxy->common.offset = 0x0;proxy->common.size = 0x1000;proxy->common.type = VIRTIO_PCI_CAP_COMMON_CFG;proxy->isr.offset = 0x1000;proxy->isr.size = 0x1000;proxy->isr.type = VIRTIO_PCI_CAP_ISR_CFG;proxy->device.offset = 0x2000;proxy->device.size = 0x1000;proxy->device.type = VIRTIO_PCI_CAP_DEVICE_CFG;proxy->notify.offset = 0x3000;proxy->notify.size = virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX;proxy->notify.type = VIRTIO_PCI_CAP_NOTIFY_CFG;proxy->notify_pio.offset = 0x0;proxy->notify_pio.size = 0x4;proxy->notify_pio.type = VIRTIO_PCI_CAP_NOTIFY_CFG;

VirtIOPCIRegion保存了VirtIOPCIProxy设备modern MMIO的相关信息。如VirtIOProxy的modern MMIO中，最开始的区域是common区域，其大小为0x1000，范围是[0x0, 0x1000)；接着是isr区域，大小也是0x1000，范围是[0x1000, 0x2000)；然后是device区域，其大小仍然是0x1000，范围是[0x2000,0x3000)；最后是notify区域，其大小是virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX，范围是[0x3000, 0x3000+virtio_pci_queue_mem_mult(proxy) * VIRTIO_QUEUE_MAX)。

（4）VirtIOPCIProxy的modern MMIO对应的MemoryRegion存放在VirtIOPCIProxy的modern_bar成员中；它还有一个MemoryRegion存放在modern_cfg成员中（这部分老版本代码有，新版本代码已经没有了）。代码片段如下：

    /* subclasses can enforce modern, so do this unconditionally */memory_region_init(&proxy->modern_bar, OBJECT(proxy), "virtio-pci",/* PCI BAR regions must be powers of 2 */pow2ceil(proxy->notify.offset + proxy->notify.size));if (proxy->disable_legacy == ON_OFF_AUTO_AUTO) {proxy->disable_legacy = pcie_port ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF;}if (!virtio_pci_modern(proxy) && !virtio_pci_legacy(proxy)) {error_setg(errp, "device cannot work as neither modern nor legacy mode"" is enabled");error_append_hint(errp, "Set either disable-modern or disable-legacy"" to off\n");return;}

（5）virtio_pci_realize函数会调用virtio_pci_bus_new函数创建virtio-bus，挂载到当前的virtio PCI代理设备下面。代码片段如下：

    virtio_pci_bus_new(&proxy->bus, sizeof(proxy->bus), proxy);

（6）virtio_pci_realize函数在最后调用了k->realize函数指针所指向的函数。由于k是VirtioPCIClass类型，因此根据前表

	realize函数	parent_dc_realize函数
DeviceClass	virtio_pci_dc_realize
PCIDeviceClass	virtio_pci_realize
VirtioPCIClass	virtio_balloon_pci_realize	pci_qdev_realize

因此k->realize函数指针实际指向了virtio_balloon_pci_realize函数。

对于virtio_balloon_pci_realize函数内容的讲解，请看下回。