//###############################################################################################
// Description:
// program for 4路PWM信号，每路以A为准，B与之互补，带死区。移相以第一路信号（EPWM1A）为基准
// $TI Release: F2833x/F2823x Header Files and Peripheral Examples V142 $
// $Release Date: July 30, 2017 $
// $Copyright: Copyright 孙川（Sun Chuan） $
//###############################################################################################
#include "DSP28x_Project.h"
void InitExInt(void);
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
void InitEPwm4Example(void);
//interrupt void epwm1_isr(void);
//interrupt void epwm2_isr(void);
//interrupt void epwm3_isr(void);
//interrupt void epwm4_isr(void);
// Configure the period for each timer
//第一路
volatile Uint16 EPWM1_TIMER_TBPRD = 1500; // Period=1501 TBCLK counts
volatile Uint16 EPWM1_CMPA = 750; // Set 50% 占空比 for EPWM1A -> S1
//第二路
volatile Uint16 EPWM2_TIMER_TBPRD = 1500;
volatile Uint16 EPWM2_CMPA = 750;
//第三路
volatile Uint16 EPWM3_TIMER_TBPRD = 1500;
volatile Uint16 EPWM3_CMPA = 750;
//第四路
volatile Uint16 EPWM4_TIMER_TBPRD = 1500;
volatile Uint16 EPWM4_CMPA = 750;
volatile Uint16 D1 = 50; //第一路与第二路之间的移相角 若D1=x，则D1对应0.24*x度，例如x=50时，D1对应12度
volatile Uint16 D2 = 100; //第一路与第三路之间的移相角
volatile Uint16 D3 = 72; //第一路与第四路之间的移相角
#define DBTIME_FED 28 死区设置
#define DBTIME_RED 28
void main(void)
{
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();
// Step 2. Initialize GPIO:
// This example function is found in the DSP2833x_Gpio.c file and
// illustrates how to set the GPIO to it's default state.
// InitGpio(); // Disenable pull-up on GPIO0 ~ GPIO11
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3, ePWM4
// These functions are in the DSP2833x_EPwm.c file
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
InitEPwm4Gpio();
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
DINT;
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();
// Disable CPU interrupts and clear all CPU interrupt flags:
IER = 0x0000;
IFR = 0x0000;
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in DSP2833x_DefaultIsr.c.
// This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart); //烧录进Flash中运行
InitFlash();
InitExInt();
EALLOW;
PieVectTable.XINT1 = &ISRExint1;
EDIS;
PieCtrlRegs.PIEIER1.bit.INTx4= 1; // Enable XINT1 in the PIE: Group1 interrupt4
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected registers
// PieVectTable.EPWM1_INT = &epwm1_isr;
// PieVectTable.EPWM2_INT = &epwm2_isr;
// PieVectTable.EPWM3_INT = &epwm3_isr;
// PieVectTable.EPWM4_INT = &epwm4_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// For this example, only initialize the ePWM
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0; // Disable TBCLK within the ePWM
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
InitEPwm4Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1; // Enable TBCLK within the ePWM
EDIS;
// Step 5. User specific code, enable interrupts:
// Enable CPU INT3 which is connected to EPWM1-3 INT:
IER |= M_INT3;
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-4
// PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
// PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
// PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
// PieCtrlRegs.PIEIER3.bit.INTx4 = 1;
// Enable global Interrupts and higher priority real-time debug events:
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
// Step 6. IDLE loop. Just sit and loop forever (optional):
for(;;)
{
__asm(" NOP");
}
}
//interrupt void epwm1_isr(void)
//{
// //update
//
// // Clear INT flag for this timer
// EPwm1Regs.ETCLR.bit.INT = 1;
//
// // Acknowledge this interrupt to receive more interrupts from group 3
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//}
//interrupt void epwm2_isr(void)
//{
// //update
//
// // Clear INT flag for this timer
// EPwm2Regs.ETCLR.bit.INT = 1;
//
// // Acknowledge this interrupt to receive more interrupts from group 3
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//}
//
//interrupt void epwm3_isr(void)
//{
// //update
//
// // Clear INT flag for this timer
// EPwm3Regs.ETCLR.bit.INT = 1;
//
// // Acknowledge this interrupt to receive more interrupts from group 3
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//}
//interrupt void epwm4_isr(void)
//{
// //update
//
// // Clear INT flag for this timer
// EPwm4Regs.ETCLR.bit.INT = 1;
//
// // Acknowledge this interrupt to receive more interrupts from group 3
// PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//}
void InitEPwm1Example()
{
// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up_mode
EPwm1Regs.TBPRD = EPWM1_TIMER_TBPRD; // Set timer period
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Master module
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // Sync down-stream module
EPwm1Regs.TBPHS.half.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadow register load on ZERO
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm1Regs.CMPA.half.CMPA = EPWM1_CMPA; // Set compare A value
// Set actions
EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM1A on ZRO
EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM1A on CAU
// Set Dead-band module
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm1Regs.DBFED = DBTIME_FED;
EPwm1Regs.DBRED = DBTIME_RED;
// Interrupt where we will change the Compare Values
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
}
void InitEPwm2Example()
{
// Setup TBCLK
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count updown
EPwm2Regs.TBPRD = EPWM2_TIMER_TBPRD; // Set timer period
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync flow-through
EPwm2Regs.TBPHS.half.TBPHS = 1500 - D1; // Set Phase shift angle between S1 and S5 to x/1500*360 = 0.24x deg
EPwm2Regs.TBCTR = 0x0000; // Clear counter
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadow register load on ZERO
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm2Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm2Regs.CMPA.half.CMPA = EPWM2_CMPA; // Set compare A value
// Set actions
EPwm2Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM2A on ZRO
EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM2A on CAU
// Set Dead-band module
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm2Regs.DBFED = DBTIME_FED;
EPwm2Regs.DBRED = DBTIME_RED;
// Interrupt where we will change the Compare Values
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
}
void InitEPwm3Example(void)
{
// Setup TBCLK
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count updown
EPwm3Regs.TBPRD = EPWM3_TIMER_TBPRD; // Set timer period
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync flow-through
EPwm3Regs.TBPHS.half.TBPHS = 1500 - D2; // Set Phase shift angle between S1 and S6 to x/1500*360 = 0.24x deg
EPwm3Regs.TBCTR = 0x0000; // Clear counter
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadow register load on ZERO
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm3Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm3Regs.CMPA.half.CMPA = EPWM3_CMPA; // Set compare A value
// Set Actions
EPwm3Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM3A on ZRO
EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM3A on CAU
// Set Dead-band module
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm3Regs.DBFED = DBTIME_FED;
EPwm3Regs.DBRED = DBTIME_RED;
// Interrupt where we will change the Compare Values
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
}
void InitEPwm4Example(void)
{
// Setup TBCLK
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count updown
EPwm4Regs.TBPRD = EPWM4_TIMER_TBPRD; // Set timer period
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Slave module
EPwm4Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // Sync flow-through
EPwm4Regs.TBPHS.half.TBPHS = 1500 - D2 - D3; // Set Phase shift angle between S1 and S6 to x/1500*360 = 0.24x deg
EPwm4Regs.TBCTR = 0x0000; // Clear counter
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
// Setup shadow register load on ZERO
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm4Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
// Set Compare values
EPwm4Regs.CMPA.half.CMPA = EPWM4_CMPA; // Set compare A value
// Set Actions
EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET; // Set PWM4A on ZRO
EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR; // Clear PWM4A on CAU
// Set Dead-band module
EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // enable Dead-band module
EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC; // Active Hi complementary
EPwm4Regs.DBFED = DBTIME_FED;
EPwm4Regs.DBRED = DBTIME_RED;
// Interrupt where we will change the Compare Values
EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm4Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm4Regs.ETPS.bit.INTPRD = ET_1ST; // Generate INT on 1st event
}
//===========================================================================
// No more.
//===========================================================================
)
