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UMFT4222EV-D

UMFT4222EV-D - FTDI

可以下载Datasheet。

UMFT4222EVUSB2.0 to QuadSPI/I2C Bridge Development Module

Future Technology Devices International Ltd.

The UMFT4222EV is a development module which uses FTDI’s FT4222H, a Hi-Speed USB2.0 to QuadSPI/I2C Bridge in compact 32-pin QFN package. FT4222H requires an external Crystal (12MHz) for the internal PLL to operate. It supports multi-voltage IO, 3.3V, 2.5V or 1.8V. It also provides 128 Bytes one-time-programmable (OTP) memory space for storing vendor specific information. The FT4222H contains SPI/ I2C configurable interfaces. The SPI interface can be configured as master mode with single, dual, or quad bits data width transfer or slave mode with single bit data width transfer. The I2C interface can be configured as master or slave mode.

The UMFT4222EV is supplied as a small PCB which is designed to plug into a standard 0.8” wide 24 pin DIP socket. All components are Pb-free (RoHS compliant).

The UMFT4222EV has the following features:

• Single Hi-Speed USB2.0 chip (FT4222H) to flexible and configurable SPI/I2C interfaces.
• SPI interface support for Single / Dual / Quad SPI Master Mode with configurable target operating speed.
• Up to 28Mbps data transfer rate in SPI mode with quad data mode.
• Support up to 4 slave selection control pins in SPI master mode.
• Support Single SPI Slave Mode with SCK operating frequency up to 20MHz.
• SCK can support up to 40MHz in SPI master.
• I2C interface support 7-bits address and fully compatible to v2.1 and v3 specification for I2C Master/Slave Mode with configurable target operating speed for 100kbit/S standard mode, 400kbit/S fast mode 1Mbit/S Fast mode plus and 3.4Mbit/S high speed mode.

• Configurable GPIOs controlled by application software via USB bus.
• Fully support USB2.0 suspend/resume and remote wakeup.
• Support Battery Charger Detection.
• OTP memory inside for USB Vendor ID (VID), Product ID (PID), device serial number, product description string and various other vendor specific data.
• USB Power Configurations; bus-powered and self-powered.
• On board jumper for FT4222H configuration mode, USB power configuration and VCCIO source selection.
• Integrated power-on-reset circuit.
• True 3.3V CMOS drive output and TTL input. (operates down to 1.8V with external 1.8V power input to VCCIO.
• USB2.0 Low operating and suspend current; 68mA (active-typ.) and 375uA (suspend-typ).
• Configurable I/O pin output drive strength: 4 mA(min) and 16 mA(max).
• UHCI / OHCI / EHCI / XHCI host controller compatible.
• FTDI’s royalty-free Direct (D2XX) drivers eliminate the requirement for USB driver development in most cases.
• Supplied PCB designed to fit a standard 20.2mm (0.8”) wide 24 pin DIP socket. Pins are on a 2.54mm (0.1”) pitch.
• On board USB Micro-B receptacle allows module to be connected to a PC.

1 Typical Applications

• USB to single mode SPI master controller.
• USB to dual mode SPI master controller
• USB to quad mode SPI master controller
• USB to single SPI slave controller
• USB to I2C master interface controller
• USB to I2C slave interface controller
• Utilizing USB to add system modularity

• Incorporate USB interface to enable PC transfers for development system communication.
• USB Industrial Control
• USB Data Acquisition
• USB dongle implementations for Software/ Hardware Encryption and Wireless Modules
• Detect USB dedicated charging ports, to allow for high current battery charging in portable devices

1.1 Driver Support
Royalty free D2XX Direct Drivers are available for the following Operating Systems (OS):
• Windows
• Linux
• Mac
• Android (J2xx / D2xx only)

See the following website link for the full driver support list including OS versions and legacy OS.

Drivers - FTDI

D2XX Direct Drivers allow direct access to the USB device through a DLL. Application software can access the USB device through a series of DLL function calls. A support library for FT4222H, LibFT4222, must be used in conjunction with D2XX and provides high-level and convenient APIs (Application Programming Interface) to speed up user application development. For further details refer to AN_329 User Guide for LibFT4222.

User Guide for LibFT4222

Example code is also provided with the LibFT4222 download. Some D2xx direct functions can be used too. Refer to Appendix B – D2XX API support of AN_329 User Guide for LibFT4222 and reference the D2XX Programmer’s Guide document for details of those APIs which is available from the Documents section of our website.

FT4222H Software Examples - FTDI

D2XX Programmer's Guide

Programming Guides - FTDI

Please also refer to the Installation Guides webpage for details on how to install the drivers.

Installation Guides - FTDI

Please note that there is no VCP interface / drivers for FT4222H. This product can only be used with the D2xx drivers and LibFT4222 library.

1.2 Part Numbers

The following table gives details of the available UMFT4222EV.

Part Number

UMFT4222EV-D

Description

FT4222H evaluation module with D version chip.

1.3 USB Compliant
The UMFT4222EV is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID) 10007740.

2 FT4222H Features and Enhancement
Functional Integration: The FT4222H is a USB 2.0 Hi-Speed (480Mbits/s) to flexible and configurable SPI/I2C interfaces device. The FT4222H includes an integrated +1.8V and +3.3V Low Drop-Out (LDO) regulator and a 12MHz to 480MHz PLL. It also includes Power-On-Reset (POR), VBUS detection with 5V-tolerance and 128 bytes one-time-programmable (OTP) memory which simplifies external circuit design and reduces external component count.

USB2.0 Hi-Speed Device Controller: The FT4222H integrates a USB protocol engine which controls the physical Universal Transceiver Macro cell Interface (UTMI) and handles all aspects of the USB 2.0 Hi-Speed interface. The device contains one control endpoint and 4 IN and OUT endpoint pairs. These endpoints can be configured to implement up to 4 independent interfaces/applications mapped to I2C+GPIO or SPI+GPIO.

Highly Integrated USB2.0 to Configurable SPI Bridge: The FT4222H provides the bridge function between a USB2.0 and SPI Master/Slave.

The support library, LibFT4222, based on FTDI’s D2XX driver, enables easy configuration of the SPI as a master or slave. Operating clock frequency on the SPI bus, clock phase and polarity, transfer data bit width mode, and the number of slave selection controls are also configurable.

The max SPI interface operating clock can be set up to 40MHz in master mode and 20MHz in slave mode. With quad mode (4-bits) data bus width, the max data transfer throughput can be up to 28Mbps.

USB to Configurable I2C Controller: The FT4222H also provides the bridge function between a USB2.0 and an I2C Master/Slave.

The support library, LibFT4222, based on FTDI’s D2XX driver, enables easy configuration of the I2C as either a master or slave, including target operating speed and bus protocol on I2C bus.

The device can run at common I2C bus speeds, 100kbit/s standard mode (SM), 400 Kbit/s fast mode (FM), 1 Mbit/s Fast mode plus (FM+), and 3.4 Mbit/s High Speed mode (HS). Clock stretching is also supported to conform to v2.1 and v3.0 of the I2C specification.

Configurable GPIOs: The GPIOs in the FT4222H can be fully controlled by an application utility over USB. There are 4 GPIO pins that can be configured for different purposes, such as a suspend indicator output, and remote wake up input.

The signal drive strength and slew rate can be configured via USB vendor commands for different design needs.

Embedded OTP memory: The internal OTP memory in the FT4222H is used to store USB Vendor ID (VID), Product ID (PID), device serial number, product description string and various other USB configuration descriptors. With this embedded OTP memory, the device can store vendor specific information and save BOM cost. The descriptors can be programmed using the FTDI utility software called FT_PROG, which can be downloaded from FTDI Utilities on the FTDI website.

Utilities - FTDI

Power management: Fully supports USB2.0 suspend/resume and remote wakeup. The PHY will be put to a power saving mode and the clock to most of the digital circuits will be stopped when the device is suspended.

Source Power and Power Consumption: The FT4222H is capable of operating at a voltage supply +3.3V or +5.0V with a nominal operational mode current of 68mA and a nominal USB suspend mode current of 375μA. This allows greater margin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated level converter within the FT4222H allows the interface logic to run at +1.8V, 2.5V or +3.3V. (Note: External pull-ups are recommended for IO <3V3).

DS_UMFT4222EV.pdf

AN_329_User_Guide_for_LibFT4222-v1.8.pdf

1 Introduction

1.1 Overview
The FT4222H supports 4 operation modes to allow various I2C/SPI devices to be connected to USB bus. The attachable device configuration for each mode is listed below:
•Mode 0 (2 USB interfaces):
     ▪1 SPI master, SPI slave, I2C master, or I2C slave device
     ▪1 GPIO device
•Mode 1 (4 USB interfaces):
     ▪SPI master connects up to 3 SPI slave devices
     ▪1 GPIO device
•Mode 2 (4 USB interfaces):
     ▪SPI master connects up to 4 SPI slave devices
•Mode 3 (1 USB interface):
     ▪1 SPI master, SPI slave, I2C master, or I2C slave device

Operation mode is configured by DCNF0 & DCNF1 pins, please see below table for detail

Table 1.1 Chip Mode with DCNF0 and DCNF1

In mode 0 and 3, the connected device can be a SPI/I2C master or slave, depending on how an application developer initializes the FT4222H chip. Mode 1 and mode 2 are designed to connect to multiple SPI slave devices.

The FT4222H can be configured with up to 4 GPIO pins for user applications in mode 0 and mode 1, but each pin is multiplexed with interrupt/suspend out/SPI slave select/I2C functions as listed below:

•gpio0 / ss1o / scl
•gpio1 / ss2o / sda
•gpio2 / ss3o / suspend out
•gpio3 / wakeup/intr

If the FT4222H is initialized as an I2C device, with pins as shown above, the pins of gpio0 and gpio1 will be switched to scl and sda and cannot be used as GPIO.

By default, the pin for gpio2 is configured as suspend out, and the pin for gpio3 is configured as wakeup/intr. Only those configured GPIO pins can support GPIO read/set operation through the corresponding endpoint.

1.2 Scope
The guide is intended for developers who are creating applications, extending FTDI provided applications or implementing FTDI’s applications for the FT4222H.

2 Getting Started

3 Application Programming Interface (API)

3.1 Typedefs

3.2 FT4222 General Functions

3.2.1 Open and Close

3.2.2 Un-initialize

3.2.3 Set Clock

3.2.4 Get Clock

3.2.5 Set Suspend Out

3.2.6 Set Wake Up/Interrupt

3.2.7 Set Interrupt Trigger Condition

3.2.8 Get Max Transfer Size

3.2.9 Set Event Notification

Sets conditions for event notification.
An application can use this function to set up conditions which allow a thread to block until one of the conditions is met. Typically, an application will create an event, call this function, and then block on the event. When the conditions are met, the event is set, and the application thread unblocked. Usually, the event is set to notify the application to check the condition. The application needs to check the condition again before it goes to handle the condition. The API is only valid when the device acts as SPI slave and SPI slave protocol is not SPI_SLAVE_NO_PROTOCOL.

Currently, this function only supports the event below:

FT4222_EVENT_RXCHAR The event will be set when a data packet has been received by the device.

3.2.10 Get Version

3.2.11 Chip Reset

3.2.12 Get Chip Mode

3.3 SPI Master Functions

For SPI Master Single mode, all data packets are terminated with a zero-length packet. Therefore, after one data packet there will be one SOF then follows by the terminating zero-length packet then ends with another SOF. As a result, under normal conditions, these two SOF’s will take approximately 250us.

3.3.1 SPI Master Init

Initialize the FT4222H as an SPI master.
To support various types of SPI slave devices, the FT4222H SPI master is configurable using the following parameters:
•IO lines: SPI transmission lines. The FT4222H SPI supports single, dual, or quad transmission mode. An application may override this initial selection dynamically using FT4222_SPIMaster_SetLines. For example, commands might be sent in single mode, but data transferred in dual or quad mode.
•Clock divider: SPI clock rate is subject to system clock. The FT4222H SPI clock could be 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256, or 1/512 system clock rate.
•Clock polarity: Idle high or idle low.
•Clock phase: Data is sampled on the leading (first) or trailing (second) clock edge.
•Slave selection output pins: Select slave devices by ss0o, ss1o, ss2o, ss3o. The default slave selection is active low.
•There is only one setting stored in the MCU. If there are multi-SPI masters to be initialized, keep all settings the same, including ssoMap.

3.3.2 SPI Master Set Lines

3.3.3 SPI Master Set Mode

3.3.4 SPI Master Set Chip Select

3.3.5 SPI Master Single Read

3.3.6 SPI Master Single Write

3.3.7 SPI Master Single Read and Write

Under SPI single mode, full-duplex write data to and read data from an SPI slave.
The standard SPI protocol simultaneously sends data onto the MOSI data line and receives data from the MISO line.

uint8 sendData[2];
uint8 readData[2];

sendData[0] = 0x05; // read status command
sendData[1] = 0xFF; // a dummy byte,

ft4222Status = FT4222_SPIMaster_SingleReadWrite(ftHandle, &readData[0], &sendData[0], 2, &sizeTransferred, true);

3.3.8 SPI Master Multi Read and Write

Under SPI dual or quad mode, write data to and read data from an SPI slave.

Figure 3.2 illustrates the dual-SPI protocol supported by the FT4222H SPI master. It is a mixed protocol initiated with a single write transmission, which may be an SPI command and dummy cycles, and followed by dual-write and dual-read transmission that use 2 signals in parallel for the data. All three parts of the protocol are optional. For example, developers can ignore the multi-read part by setting multiReadBytes=0.

Figure 3.2 Dual SPI communications

Avoid I/O conflict from multiWriteBytes state to multiReadBytes state. When SPI finishes multiWriteBytes state, I/O pins (Dual mode:mosi/miso, Quad mode:mosi/miso/io2/io3) will keep the output state for T2 period of time and then change to input state.

This table only takes effect on CLK division >=8. If CLK division is equal to 2 or 4, the time for T2 and T3 is very close and SPI Slave is hard to switch the I/O in such a short time.

3.4 SPI Slave Functions

The FT4222H can be initialized as an SPI slave under mode 0 to mode 3. As an SPI slave, the FT4222H only supports the standard single SPI transfer.

SPI Slave function is not suitable on Android system. Garbage collection is a form of automatic memory management. When garbage collection happens, it does not emit bulk-in packet and RX data may be lost during this period of time.

A USB-SPI bridge usually faces the challenge that USB cannot guarantee the throughput for each endpoint, but SPI requires data transmission at a steady rate. It is highly possible when an SPI master starts to request data from a USB-SPI slave bridge device, the data has not arrived from the USB host side yet. In addition, SPI does not have a standard protocol to allow the master side to check the status of the slave side. The protocol is usually provided by an SPI slave device on its own, which makes the SPI master device communicate with the slave device by its specified commands.

There are three methods to access FT4222 SPI Slave function.
•SPI_SLAVE_WITH_PROTOCOL
•SPI_SLAVE_NO_ACK
•SPI_SLAVE_NO_PROTOCOL

With all the SPI Slave operational modes listed, the support library will always add a dummy byte of “0x00” as the first byte for every transmission. This is an internal sync byte that is needs to be removed by the SPI Master.

SPI_SLAVE_WITH_PROTOCOL

The FT4222H and LibFT4222 design have implemented an SPI slave protocol which must be used to handle the integrity of data transmission. The API “FT4222_SPISlave_Init” is used to initialize the slave with this mode.

In this protocol, a master starts an SPI transaction by sending a packet in the format illustrated below. The Sync Word “0x5A” is fixed with this slave mode and user applications do not need to do any operations to add or remove the Sync Word. It is done by the support library.

SN stands for serial number. It is monotonically increased and helps to identify packets. Size is a two-byte field, which is the size of the data field in big-endian order. The Checksum is the summation of all data fields’ lower two bytes starting from the first byte, the sync word, to the latest data byte.

The checksum is in big-endian order as well. When the slave, FT4222H, receives the transfer request from the master, it will respond with an ACK. The master can confirm the transaction succeeded when it receives the ACK from the slave.

When SPI Slave receives the Master transfer request, it will check if the format and checksum are correct. If the answer is yes, the support-lib will send the response ACK automatically, grab the data from the packet and send it to application.

Here is an example of an ACK packet. The SN field of the ACK packet identifies which request it corresponds to. An ACK packet has no data therefore the Size field should be 0.

If the SPI master does not receive the ACK response from the slave, it should send its request again.

When the FT4222H SPI slave wants to send data to the master, which may be requested by the master, it just sends a transfer request in the same protocol format as shown in Figure 3.4.

In this case, it is not necessary to append any header while API FT4222_SPISlave_Write is called.
The encapsulation of header is done by support-lib.

SPI_SLAVE_NO_ACK

This option is to reduce the complication of SPI_SLAVE_WITH PROTOCOL.

It removes the ACK response from the Slave.

SPI_SLAVE_NO_PROTOCOL

This option provides no protocol for SPI Slave function, and it is configured and initialized with the API FT4222_SPISlave_InitEx.

In this SPI Slave operational mode, the Sync Word “0x5A” is not inserted. And there is no additional process in support-lib.

Users can design own protocol(s) to communicate with a SPI master.

3.4.1 SPI Slave Init

Parameters:

ftHandle, Handle of the device.

Return Value:
FT4222_OK if successful, otherwise the return value is an FT error code.

3.4.2 SPI Slave Init extend function

Parameters:

ftHandle, Handle of the device.

protocolOpt,

SPI SLAVE protocol could be:
•SPI_SLAVE_WITH_PROTOCOL
With the full SPI SLAVE PROTOCOL supported. Refer to chapter 3.4
•SPI_SLAVE_NO_PROTOCOL
Remove SPI SLAVE protocol, users can design their own protocol.
•SPI_SLAVE_NO_ACK
Retain SPI SLAVE protocol but remove command ‘ACK’

3.4.3 SPI Slave Set mode function

Set SPI slave CPOL and CPHA. The Default value of CPOL is CLK_IDLE_LOW, default value of CPHA is CLK_LEADING.

3.4.4 SPI Slave Get Rx Status

3.4.5 SPI Slave Read

3.4.6 SPI Slave Write

3.5 SPI General Functions

3.5.1 SPI Reset Transaction

Reset the SPI transaction. It would purge receive and transmit buffers in the device and reset the transaction state. D2XX has a similar function (FT_PURGE) but strongly recommend to use FT4222_SPI_ResetTransaction.

3.5.2 SPI Reset

Reset the SPI master or slave device. If the SPI bus encounters errors or works abnormally, this function will reset the SPI device. It is not necessary to call SPI init function again after calling this reset function. It remains all original setting of SPI.

3.5.3 SPI Set Driving Strength

For the FT4222H SPI, set the driving strength of clk, io, and sso pins. The default driving strength of all SPI pins are 4MA. DS_4MA is adopted mostly. Unless there is some hardware wiring requirement for device, set driving strength to 4MA is enough.

3.6 I2C Master Functions

I2C (Inter Integrated Circuit) is a multi-master serial bus invented by Philips. I2C uses two bi-directional open-drain wires called serial data (SDA) and serial clock (SCL). Common I²C bus speeds are the 100 kbit/s standard mode (SM), 400 kbit/s fast mode (FM), 1 Mbit/s Fast mode plus (FM+), and 3.4 Mbit/s High Speed mode (HS)

The FT4222H device can be initialized as either an I2C master or I2C slave under mode 0 and mode 3. Here is a brief overview of FT4222H I2C features:

•Fully compatible to I2C v2.1 and v3 specification
•7-bit address support
•Support 4 speed configurations: 100KHz(SM), 400KHz(FM), 1MHz(FM+), and 3.4MHz(HS).
•Clock stretching support in both master and slave mode.

3.6.1 I2C Master Init

3.6.2 I2C Master Read

3.6.3 I2C Master Write

3.6.4 I2C Master Write Extension

I²C defines basic types of transactions, each of which begins with a START and ends with a STOP:

• Single message where a master writes data to a slave.
• Single message where a master reads data from a slave.
• Combined format, where a master issues at least two reads or writes to one or more slaves.

In a combined transaction, each read or write begins with a START and the slave address. The START conditions after the first are also called repeated START bits. Repeated STARTs are not preceded by STOP conditions, which is how slaves know that the next message is part of the same transaction.

3.6.5 I2C Master Read Extension

Read data from the specified I2C slave device with the specified I2C condition.
This function is supported by the Revision B FT4222H or later.

I²C combined message support

In a combined message, each read or write begins with a START and the slave address. After the first START, the subsequent starts are referred to as repeated START bits; repeated START bits are not preceded by STOP bits, which indicate to the slave the next transfer is part of the same message.

SR = repeated START condition

3.6.6 I2C Master GetStatus

Read the status of the I2C master controller. This can be used to poll a slave after I2C transmission is complete.

controllerStatus

Address of byte to receive status flags:
bit 0: controller busy: all other status bits invalid
bit 1: error condition
bit 2: slave address was not acknowledged during last operation
bit 3: data not acknowledged during last operation
bit 4: arbitration lost during last operation
bit 5: controller idle
bit 6: bus busy
The header file provides convenience macros (such as I2CM_BUS_BUSY) to test these bits.

3.6.7 I2C Master Reset

Reset the I2C master device.
If the I2C bus encounters errors or works abnormally, this function will reset the I2C device. It is not necessary to call I2CMaster_Init again after calling this reset function. This function will maintain the original I2C master setting and clear all cache in the device. D2XX has a similar function (FT_PURGE) but strongly recommend to use FT4222_I2CMaster_Reset.

3.6.8 I2C Master Reset Bus

If the data line (SDA) is pulled LOW by slave device, this API will send nine SCK clocks from master to recover I2C bus. The slave device will release data line (SDA) when it receives the nine clocks from master. If data line cannot be released by this API, HW reset or cycle power is another solution.

3.7 I2C Slave Functions

The FT4222H device can be initialized as an I2C slave under mode 0 and mode 3. It conforms to v2.1 and v3.0 of the I2C specification and supports all the transmission modes: Standard, Fast, Fast-plus and High Speed.

When the I2C slave receives data from the I2C bus, it will keep the data in its internal receive buffer (256 bytes), and then send the data to the USB host through IN packets.

When data is requested by an I2C master, data will be moved from an OUT packet to the transmit register directly.

3.7.1 I2C Slave Init

Initialize FT4222H as an I2C slave. After FT4222_I2CSlave_Init, I2C slave address is reset to 0x40.

3.7.2 I2C Slave Get Address

3.7.3 I2C Slave Set Address

3.7.4 I2C Slave Get Rx Status

3.7.5 I2C Slave Read

3.7.6 I2C Slave Write

Write data to the buffer of I2C slave device.

3.7.7 I2C Slave Reset

3.7.8 I2C Slave Clock Stretch

Enable or disable Clock Stretch. The default setting of clock stretching is disabled.

Clock stretch is as a flow-control mechanism for slaves. An addressed slave device may hold the clock line (SCL) low after receiving (or sending) a byte, indicating that it is not yet ready to process more data. The master that is communicating with the slave may not finish the transmission of the current bit but must wait until the clock line goes high.

3.7.9 I2C Slave Set Response Word

This function only takes effect when Clock Stretch is disabled. When data is requested by an I2C master and the device is not ready to respond, the device will respond a default value. Default value is 0xFF. This function can be used to set the response word.

3.8 GPIO Functions

The FT4222H contains 4 GPIO. When the USB GPIO interface is supported, chip mode 0 and mode 1, LibFT4222 helps application developers to control GPIO directly. However, each GPIO pin is multiplexed with interrupt/suspend out/SPI slave select/I2C functions as listed below:

•gpio0 / ss1o / scl
•gpio1 / ss2o / sda
•gpio2 / ss3o / suspend out
•gpio3 / wakeup/intr

3.8.1 GPIO Init

3.8.2 GPIO Read

3.8.3 GPIO Write

3.8.4 GPIO Set Input Trigger

3.8.5 GPIO Get Trigger Status

3.8.7 GPIO Set WaveForm Mode

3.8.6 GPIO Read Trigger Queue

3.8.7 GPIO Set WaveForm Mode

4 Contact Information

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