基于FPGA的频率计与串口通信（二）

接上篇，本文章展示基于FPGA的频率计与串口通信项目部分核心代码。

顶层文件

top.bdf

//#pragma file_not_in_maxplusii_format
(header "graphic" (version "1.3"))
(pin(input)(rect 80 328 248 344)(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))(text "clk" (rect 5 0 19 12)(font "Arial" ))(pt 168 8)(drawing(line (pt 92 12)(pt 117 12)(line_width 1))(line (pt 92 4)(pt 117 4)(line_width 1))(line (pt 121 8)(pt 168 8)(line_width 1))(line (pt 92 12)(pt 92 4)(line_width 1))(line (pt 117 4)(pt 121 8)(line_width 1))(line (pt 117 12)(pt 121 8)(line_width 1)))(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))(annotation_block (location)(rect 32 328 80 344))
)
(pin(input)(rect 80 344 248 360)(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))(text "inclk" (rect 5 0 27 12)(font "Arial" ))(pt 168 8)(drawing(line (pt 92 12)(pt 117 12)(line_width 1))(line (pt 92 4)(pt 117 4)(line_width 1))(line (pt 121 8)(pt 168 8)(line_width 1))(line (pt 92 12)(pt 92 4)(line_width 1))(line (pt 117 4)(pt 121 8)(line_width 1))(line (pt 117 12)(pt 121 8)(line_width 1)))(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))(annotation_block (location)(rect 32 344 80 360))
)
(pin(input)(rect 72 280 240 296)(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))(text "rst" (rect 5 0 17 12)(font "Arial" ))(pt 168 8)(drawing(line (pt 92 12)(pt 117 12)(line_width 1))(line (pt 92 4)(pt 117 4)(line_width 1))(line (pt 121 8)(pt 168 8)(line_width 1))(line (pt 92 12)(pt 92 4)(line_width 1))(line (pt 117 4)(pt 121 8)(line_width 1))(line (pt 117 12)(pt 121 8)(line_width 1)))(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))(annotation_block (location)(rect 24 280 72 296))
)
(pin(input)(rect 32 376 200 392)(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))(text "key" (rect 5 0 23 12)(font "Arial" ))(pt 168 8)(drawing(line (pt 92 12)(pt 117 12)(line_width 1))(line (pt 92 4)(pt 117 4)(line_width 1))(line (pt 121 8)(pt 168 8)(line_width 1))(line (pt 92 12)(pt 92 4)(line_width 1))(line (pt 117 4)(pt 121 8)(line_width 1))(line (pt 117 12)(pt 121 8)(line_width 1)))(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))(annotation_block (location)(rect -16 376 32 392))
)
(pin(output)(rect 872 312 1048 328)(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))(text "txd" (rect 90 0 105 12)(font "Arial" ))(pt 0 8)(drawing(line (pt 0 8)(pt 52 8)(line_width 1))(line (pt 52 4)(pt 78 4)(line_width 1))(line (pt 52 12)(pt 78 12)(line_width 1))(line (pt 52 12)(pt 52 4)(line_width 1))(line (pt 78 4)(pt 82 8)(line_width 1))(line (pt 82 8)(pt 78 12)(line_width 1))(line (pt 78 12)(pt 82 8)(line_width 1)))(annotation_block (location)(rect 1064 328 1112 344))
)
(pin(output)(rect 496 232 672 248)(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))(text "outclk" (rect 90 0 119 12)(font "Arial" ))(pt 0 8)(drawing(line (pt 0 8)(pt 52 8)(line_width 1))(line (pt 52 4)(pt 78 4)(line_width 1))(line (pt 52 12)(pt 78 12)(line_width 1))(line (pt 52 12)(pt 52 4)(line_width 1))(line (pt 78 4)(pt 82 8)(line_width 1))(line (pt 82 8)(pt 78 12)(line_width 1))(line (pt 78 12)(pt 82 8)(line_width 1)))(annotation_block (location)(rect 672 248 720 264))
)
(pin(output)(rect 512 168 688 184)(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))(text "seg_duan[7..0]" (rect 90 0 163 12)(font "Arial" ))(pt 0 8)(drawing(line (pt 0 8)(pt 52 8)(line_width 1))(line (pt 52 4)(pt 78 4)(line_width 1))(line (pt 52 12)(pt 78 12)(line_width 1))(line (pt 52 12)(pt 52 4)(line_width 1))(line (pt 78 4)(pt 82 8)(line_width 1))(line (pt 82 8)(pt 78 12)(line_width 1))(line (pt 78 12)(pt 82 8)(line_width 1)))(annotation_block (location)(rect 688 184 744 296))
)
(pin(output)(rect 536 200 712 216)(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))(text "seg_wei[7..0]" (rect 90 0 154 12)(font "Arial" ))(pt 0 8)(drawing(line (pt 0 8)(pt 52 8)(line_width 1))(line (pt 52 4)(pt 78 4)(line_width 1))(line (pt 52 12)(pt 78 12)(line_width 1))(line (pt 52 12)(pt 52 4)(line_width 1))(line (pt 78 4)(pt 82 8)(line_width 1))(line (pt 82 8)(pt 78 12)(line_width 1))(line (pt 78 12)(pt 82 8)(line_width 1)))(annotation_block (location)(rect 712 216 768 328))
)
(symbol(rect 648 288 824 544)(text "uart" (rect 5 0 23 12)(font "Arial" ))(text "inst" (rect 8 240 25 252)(font "Arial" ))(port(pt 0 32)(input)(text "clk" (rect 0 0 14 12)(font "Arial" ))(text "clk" (rect 21 27 35 39)(font "Arial" ))(line (pt 0 32)(pt 16 32)(line_width 1)))(port(pt 0 48)(input)(text "rst" (rect 0 0 12 12)(font "Arial" ))(text "rst" (rect 21 43 33 55)(font "Arial" ))(line (pt 0 48)(pt 16 48)(line_width 1)))(port(pt 0 64)(input)(text "rxd" (rect 0 0 15 12)(font "Arial" ))(text "rxd" (rect 21 59 36 71)(font "Arial" ))(line (pt 0 64)(pt 16 64)(line_width 1)))(port(pt 0 80)(input)(text "start" (rect 0 0 22 12)(font "Arial" ))(text "start" (rect 21 75 43 87)(font "Arial" ))(line (pt 0 80)(pt 16 80)(line_width 1)))(port(pt 0 96)(input)(text "data_cnt[3..0]" (rect 0 0 68 12)(font "Arial" ))(text "data_cnt[3..0]" (rect 21 91 89 103)(font "Arial" ))(line (pt 0 96)(pt 16 96)(line_width 3)))(port(pt 0 112)(input)(text "count1[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count1[7..0]" (rect 21 107 80 119)(font "Arial" ))(line (pt 0 112)(pt 16 112)(line_width 3)))(port(pt 0 128)(input)(text "count2[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count2[7..0]" (rect 21 123 80 135)(font "Arial" ))(line (pt 0 128)(pt 16 128)(line_width 3)))(port(pt 0 144)(input)(text "count3[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count3[7..0]" (rect 21 139 80 151)(font "Arial" ))(line (pt 0 144)(pt 16 144)(line_width 3)))(port(pt 0 160)(input)(text "count4[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count4[7..0]" (rect 21 155 80 167)(font "Arial" ))(line (pt 0 160)(pt 16 160)(line_width 3)))(port(pt 0 176)(input)(text "count5[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count5[7..0]" (rect 21 171 80 183)(font "Arial" ))(line (pt 0 176)(pt 16 176)(line_width 3)))(port(pt 0 192)(input)(text "count6[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count6[7..0]" (rect 21 187 80 199)(font "Arial" ))(line (pt 0 192)(pt 16 192)(line_width 3)))(port(pt 0 208)(input)(text "count7[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count7[7..0]" (rect 21 203 80 215)(font "Arial" ))(line (pt 0 208)(pt 16 208)(line_width 3)))(port(pt 0 224)(input)(text "count8[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count8[7..0]" (rect 21 219 80 231)(font "Arial" ))(line (pt 0 224)(pt 16 224)(line_width 3)))(port(pt 176 32)(output)(text "txd" (rect 0 0 15 12)(font "Arial" ))(text "txd" (rect 140 27 155 39)(font "Arial" ))(line (pt 176 32)(pt 160 32)(line_width 1)))(port(pt 176 48)(output)(text "send_finish" (rect 0 0 56 12)(font "Arial" ))(text "send_finish" (rect 99 43 155 55)(font "Arial" ))(line (pt 176 48)(pt 160 48)(line_width 1)))(parameter"div_par""0000000101000101"""(type "PARAMETER_UNSIGNED_BIN")	)(drawing(rectangle (rect 16 16 160 240)(line_width 1)))(annotation_block (parameter)(rect 776 256 1024 288))
)
(symbol(rect 288 304 472 560)(text "text_f" (rect 5 0 34 12)(font "Arial" ))(text "inst4" (rect 8 240 31 252)(font "Arial" ))(port(pt 0 32)(input)(text "sysclk" (rect 0 0 33 12)(font "Arial" ))(text "sysclk" (rect 21 27 54 39)(font "Arial" ))(line (pt 0 32)(pt 16 32)(line_width 1)))(port(pt 0 48)(input)(text "inclk" (rect 0 0 22 12)(font "Arial" ))(text "inclk" (rect 21 43 43 55)(font "Arial" ))(line (pt 0 48)(pt 16 48)(line_width 1)))(port(pt 0 64)(input)(text "send_finish" (rect 0 0 56 12)(font "Arial" ))(text "send_finish" (rect 21 59 77 71)(font "Arial" ))(line (pt 0 64)(pt 16 64)(line_width 1)))(port(pt 0 80)(input)(text "key" (rect 0 0 18 12)(font "Arial" ))(text "key" (rect 21 75 39 87)(font "Arial" ))(line (pt 0 80)(pt 16 80)(line_width 1)))(port(pt 184 32)(output)(text "outclk" (rect 0 0 29 12)(font "Arial" ))(text "outclk" (rect 134 27 163 39)(font "Arial" ))(line (pt 184 32)(pt 168 32)(line_width 1)))(port(pt 184 48)(output)(text "seg_duan[7..0]" (rect 0 0 73 12)(font "Arial" ))(text "seg_duan[7..0]" (rect 90 43 163 55)(font "Arial" ))(line (pt 184 48)(pt 168 48)(line_width 3)))(port(pt 184 64)(output)(text "seg_wei[7..0]" (rect 0 0 64 12)(font "Arial" ))(text "seg_wei[7..0]" (rect 99 59 163 71)(font "Arial" ))(line (pt 184 64)(pt 168 64)(line_width 3)))(port(pt 184 80)(output)(text "start" (rect 0 0 22 12)(font "Arial" ))(text "start" (rect 141 75 163 87)(font "Arial" ))(line (pt 184 80)(pt 168 80)(line_width 1)))(port(pt 184 96)(output)(text "count1[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count1[7..0]" (rect 104 91 163 103)(font "Arial" ))(line (pt 184 96)(pt 168 96)(line_width 3)))(port(pt 184 112)(output)(text "count2[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count2[7..0]" (rect 104 107 163 119)(font "Arial" ))(line (pt 184 112)(pt 168 112)(line_width 3)))(port(pt 184 128)(output)(text "count3[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count3[7..0]" (rect 104 123 163 135)(font "Arial" ))(line (pt 184 128)(pt 168 128)(line_width 3)))(port(pt 184 144)(output)(text "count4[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count4[7..0]" (rect 104 139 163 151)(font "Arial" ))(line (pt 184 144)(pt 168 144)(line_width 3)))(port(pt 184 160)(output)(text "count5[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count5[7..0]" (rect 104 155 163 167)(font "Arial" ))(line (pt 184 160)(pt 168 160)(line_width 3)))(port(pt 184 176)(output)(text "count6[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count6[7..0]" (rect 104 171 163 183)(font "Arial" ))(line (pt 184 176)(pt 168 176)(line_width 3)))(port(pt 184 192)(output)(text "count7[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count7[7..0]" (rect 104 187 163 199)(font "Arial" ))(line (pt 184 192)(pt 168 192)(line_width 3)))(port(pt 184 208)(output)(text "count8[7..0]" (rect 0 0 59 12)(font "Arial" ))(text "count8[7..0]" (rect 104 203 163 215)(font "Arial" ))(line (pt 184 208)(pt 168 208)(line_width 3)))(drawing(rectangle (rect 16 16 168 240)(line_width 1)))
)
(connector(pt 288 352)(pt 248 352)
)
(connector(pt 576 224)(pt 280 224)
)
(connector(pt 280 224)(pt 280 336)
)
(connector(pt 288 368)(pt 264 368)
)
(connector(pt 264 592)(pt 264 368)
)
(connector(pt 264 592)(pt 856 592)
)
(connector(pt 240 288)(pt 560 288)
)
(connector(pt 472 336)(pt 496 336)
)
(connector(pt 496 336)(pt 496 240)
)
(connector(pt 472 352)(pt 512 352)(bus)
)
(connector(pt 536 368)(pt 536 208)(bus)
)
(connector(pt 576 320)(pt 648 320)
)
(connector(pt 576 224)(pt 576 320)
)
(connector(pt 856 336)(pt 824 336)
)
(connector(pt 856 592)(pt 856 336)
)
(connector(pt 560 336)(pt 648 336)
)
(connector(pt 560 288)(pt 560 336)
)
(connector(pt 824 320)(pt 872 320)
)
(connector(pt 472 368)(pt 536 368)(bus)
)
(connector(pt 624 384)(pt 472 384)
)
(connector(pt 624 384)(pt 624 368)
)
(connector(pt 648 368)(pt 624 368)
)
(connector(pt 472 400)(pt 648 400)(bus)
)
(connector(pt 472 416)(pt 648 416)(bus)
)
(connector(pt 472 432)(pt 648 432)(bus)
)
(connector(pt 472 448)(pt 648 448)(bus)
)
(connector(pt 648 464)(pt 472 464)(bus)
)
(connector(pt 472 480)(pt 648 480)(bus)
)
(connector(pt 648 496)(pt 472 496)(bus)
)
(connector(pt 472 512)(pt 648 512)(bus)
)
(connector(pt 512 176)(pt 512 352)(bus)
)
(connector(pt 288 384)(pt 200 384)
)
(junction (pt 280 336))

该文件为工程的顶层文件，相当于C语言中的主函数，下面的文件相当C语言中的子函数。

频率采集模块

test_f.v

module text_f(sysclk,inclk,outclk,seg_duan,seg_wei,start,send_finish,key,count1,count2,count3,count4,count5,count6,count7,count8);
input        sysclk,inclk;//系统时钟
output outclk;
output  start;
input   send_finish;
input   key;
output [7:0] seg_duan,seg_wei;//输入时钟
output [7:0] count1;
output [7:0] count2;
output [7:0] count3;
output [7:0] count4;
output [7:0] count5;
output [7:0] count6;
output [7:0] count7;
output [7:0] count8;
wire         sysclk,inclk;//系统时钟//输入时钟
reg start;
reg [24:0] clk_counter;//时钟计数
reg clk_div;//分频后的时钟
reg    [7:0] seg_duan,seg_wei;//输入时钟
reg [7:0] data;
reg [3:0] counter1,counter2,counter3,counter4,counter5,counter6,counter7,counter8;
reg [7:0] count1,count2,count3,count4,count5,count6,count7,count8;
reg [3:0] count1_seg,count2_seg,count3_seg,count4_seg,count5_seg,count6_seg,count7_seg,count8_seg;
reg [14:0] counter1_clk;
reg [15:0] counter2_clk;
reg test_clk1;
reg test_clk2;
reg outclk;
/***********************产生测试时钟1**************************************/
always @(posedge sysclk)begin if(counter1_clk == 15'b110_0001_1010_1000)begintest_clk1<=~test_clk1;//500HZcounter1_clk<=15'b0;endelsecounter1_clk<=counter1_clk+1'b1;end
/***********************产生测试时钟2**************************************/
always @(posedge sysclk)begin if(counter2_clk == 16'd50000)begintest_clk2<=~test_clk2;//250HZcounter2_clk<=16'b0;endelsecounter2_clk<=counter2_clk+1'b1;end
/***********************选择输出的时钟**************************************/
always @(key)begin if(key == 1'b1)outclk <= test_clk1;elseoutclk <= test_clk2;end/**********************产生1HZ的时钟************************************/
always @(posedge sysclk)begin if(clk_counter==25'b1_0111_1101_0111_1000_0100_0000)beginclk_div<=~clk_div;clk_counter<=25'b0;endelseclk_counter<=clk_counter+1'b1;end
/*********************测试待测信号***********************************/
always @(posedge outclk)begin if(clk_div)beginstart <= 1'b0;if(counter1==4'b1001)begin counter1<=4'b0;counter2<=counter2+1'b1;if(counter2==4'b1001)begin counter2<=4'b0;counter3<=counter3+1'b1;if(counter3==4'b1001)begin counter3<=4'b0;counter4<=counter4+1'b1;if(counter4==4'b1001)begin counter4<=4'b0;counter5<=counter5+1'b1;if(counter5==4'b1001)begin counter5<=4'b0;counter6<=counter6+1'b1;if(counter6==4'b1001)begincounter6<=4'b0;counter7<=counter7+1'b1;if(counter7==4'b1001)begin counter7<=4'b0;counter8<=counter8+1'b1;if(counter8==4'b1001)begincounter8<=4'b0;endend end  end end end end endelsecounter1<=counter1+1'b1;endelse
/*******************测试结果寄存********************************/beginstart <= 1'b1;if(counter1!=4'b0000|counter2!=4'b0000!=4'b0000|counter3!=4'b0000|counter4!=4'b0000|counter5!=4'b0000|counter6!=4'b0000|counter7!=4'b0000|counter8!=4'b0000)begin count1<=counter1+8'd48;count2<=counter2+8'd48;count3<=counter3+8'd48;count4<=counter4+8'd48;count5<=counter5+8'd48;count6<=counter6+8'd48;count7<=counter7+8'd48;count8<=counter8+8'd48;count1_seg<=counter1;count2_seg<=counter2;count3_seg<=counter3;count4_seg<=counter4;count5_seg<=counter5;count6_seg<=counter6;count7_seg<=counter7;count8_seg<=counter8;counter1<=4'b0000;counter2<=4'b0000;counter3<=4'b0000;counter4<=4'b0000;counter5<=4'b0000;counter6<=4'b0000;counter7<=4'b0000;counter8<=4'b0000;endendend/*****************测试结果数码管显示*************************/
always @(clk_counter , count1_seg , count2_seg , count3_seg , count4_seg , count5_seg , count6_seg , count7_seg , count8_seg,data)begincase(clk_counter[15:13])//数码管位扫描3'b000:begin seg_wei<=8'b1111_1110;data<=count1_seg;end 3'b001:begin seg_wei<=8'b1111_1101;data<=count2_seg;end3'b010:begin seg_wei<=8'b1111_1011;data<=count3_seg;end 3'b011:begin seg_wei<=8'b1111_0111;data<=count4_seg;end default:begin seg_wei<=8'bx;data<=4'bx;end endcasecase(data[3:0])//数码管显示4'b0000:begin seg_duan<=8'b1100_0000;end//04'b0001:begin seg_duan<=8'b1111_1001;end//14'b0010:begin seg_duan<=8'b1010_0100;end//24'b0011:begin seg_duan<=8'b1011_0000;end//34'b0100:begin seg_duan<=8'b1001_1001;end//4default:seg_duan<=8'bx;endcaseendendmodule

串口模块

uart.v

//串口通信__FPGA和上位机通信(波特率：9600bps,10个bit是1位起始位，8个数据位，1个结束)

module uart(clk,rst,rxd,txd,start,          data_cnt,       count1,count2,count3,count4,count5,count6,count7,count8,send_finish);input       clk;                //系统50MHZ时钟
input       rst;                //复位
input       rxd;                //串行数据接收端
output      txd;                //串行数据发送端
input       start;              //开始采集信号
input[3:0]  data_cnt;         //数据位标志
output      send_finish;        //发送完成标志
input [7:0] count1;
input [7:0] count2;
input [7:0] count3;
input [7:0] count4;
input [7:0] count5;
input [7:0] count6;
input [7:0] count7;
input [7:0] count8;reg[15:0]   div_reg;        //分频计数器，分频值由波特率决定。分频后得到频率8倍波特率的时钟
reg[2:0]    div8_tras_reg;  //该寄存器的计数值对应发送时当前位于的时隙数
reg[3:0]    state_tras;     //发送状态寄存器
reg         clkbaud_tras;   //以波特率为频率的发送使能信号
reg         clkbaud8x;      //以8倍波特率为频率的时钟，它的作用是将发送或接受一个bit的时钟周期分为8个时隙
reg         trasstart;      //开始发送标志
reg			send_finish;reg         txd_reg;        //发送寄存器
reg[7:0]    rxd_buf;        //接受数据缓存
reg[7:0]    txd_buf;        //发送数据缓存
reg[3:0]    send_state;     //发送状态寄存器
parameter   div_par=16'h145;
//分频参数，其值由对应的波特率计算而得，按此参数分频的时钟频率是波倍特率的8	
//倍，此处值对应9600的波特率，即分频出的时钟频率是9600*8  (CLK50M)assign txd = txd_reg;
// assign send_state=data_cnt;
/*******分频得到8倍波特率的时钟*********/ 
always@(posedge clk )
beginif(!rst)div_reg<=0;else beginif(div_reg==div_par-1'b1)div_reg<=0;elsediv_reg<=div_reg+1'b1;end
endalways@(posedge clk)
beginif(!rst)clkbaud8x<=0;else if(div_reg==div_par-1'b1)clkbaud8x<=~clkbaud8x;//分频得到8倍波特率的时钟:clkbaud8x
end
// *******************************/ always@(posedge clkbaud8x or negedge rst)//clkbaud8x
beginif(!rst)div8_tras_reg<=0;else if(trasstart)div8_tras_reg<=div8_tras_reg+1'b1;//发送开始后，时隙数在8倍波特率的时钟下加1循环
endalways@(div8_tras_reg)
beginif(div8_tras_reg==7)clkbaud_tras=1;//在第7个时隙，发送使能信号有效，将数据发出elseclkbaud_tras=0;
end
// *********发送数据模块***************/ 
always@(posedge clkbaud8x or negedge rst)//clkbaud8x
beginif(!rst) begintxd_reg<=1;//发送寄存器置高trasstart<=0;//开始发送标志置低txd_buf<=8'h00;//发送缓存器清零state_tras<=0;//发送状态寄存器清零send_finish <= 1'b0;send_state<=4'd0;endelseif(start == 1'b1)case(state_tras)4'b0000: begin  //发送起始位send_finish <= 1'b0;if(!trasstart&&send_state<4'd9) trasstart<=1;else if(send_state<4'd9) beginif(clkbaud_tras) begintxd_reg<=0;state_tras<=state_tras+1'b1;endendelse beginstate_tras<=0;end					end		4'b0001: begin //发送第1位if(clkbaud_tras) begintxd_reg<=txd_buf[0];txd_buf[6:0]<=txd_buf[7:1];state_tras<=state_tras+1'b1;endend4'b0010: begin //发送第2位if(clkbaud_tras) begintxd_reg<=txd_buf[0];txd_buf[6:0]<=txd_buf[7:1];state_tras<=state_tras+1'b1;endend4'b0011: begin //发送第3位if(clkbaud_tras) begintxd_reg<=txd_buf[0];txd_buf[6:0]<=txd_buf[7:1];state_tras<=state_tras+1'b1;endend4'b0100: begin //发送第4位if(clkbaud_tras) begintxd_reg<=txd_buf[0];txd_buf[6:0]<=txd_buf[7:1];state_tras<=state_tras+1'b1;endend4'b0101: begin //发送第5位if(clkbaud_tras) begintxd_reg<=txd_buf[0];txd_buf[6:0]<=txd_buf[7:1];state_tras<=state_tras+1'b1;endend4'b0110: begin //发送第6位if(clkbaud_tras) begintxd_reg<=txd_buf[0];txd_buf[6:0]<=txd_buf[7:1];state_tras<=state_tras+1'b1;endend4'b0111: begin //发送第7位if(clkbaud_tras) begintxd_reg<=txd_buf[0];txd_buf[6:0]<=txd_buf[7:1];state_tras<=state_tras+1'b1;endend4'b1000: begin //发送第8位if(clkbaud_tras) begintxd_reg<=txd_buf[0];txd_buf[6:0]<=txd_buf[7:1];state_tras<=state_tras+1'b1;endend4'b1001: begin //发送停止位if(clkbaud_tras) begintxd_reg<=1;txd_buf<=8'h00;state_tras<=state_tras+1'b1;endend4'b1111:beginif(clkbaud_tras) beginstate_tras<=state_tras+1'b1;send_state<=send_state+1'b1;trasstart<=0;case(send_state)4'b0000:txd_buf<=count8;//4'b0001:txd_buf<=count7;//4'b0010:txd_buf<=count6;//4'b0011:txd_buf<=count5;//4'b1000:begintxd_buf<=8'd10;//换行符send_finish <= 1'b1;send_state<=4'b0000;enddefault:txd_buf<=8'd0;endcaseendenddefault: beginif(clkbaud_tras) beginstate_tras<=state_tras+1'b1;trasstart<=1;endendendcase
end
endmodule

本文来自互联网用户投稿，该文观点仅代表作者本人，不代表本站立场。本站仅提供信息存储空间服务，不拥有所有权，不承担相关法律责任。如若转载，请注明出处：http://www.mzph.cn/diannao/1494.shtml

如若内容造成侵权/违法违规/事实不符，请联系多彩编程网进行投诉反馈email:809451989@qq.com，一经查实，立即删除！

相关文章

Spark---RDD的创建分类和基础操作算子详解

Spark---RDD的创建分类和基础操作算子详解

一、RDD的创建 原生api提供了两种创建方式&#xff0c;一种就是读取文件textFile&#xff0c;还有一种就是加载一个scala集合parallelize。当然&#xff0c;也可以通过transformation算子来创建的RDD。 //创建RDD//加载数据&#xff0c;textFile&#xff08;参数1&#xff0c;…
阅读更多...
新牛市新方向：探索加密货币生态的未来

新牛市新方向：探索加密货币生态的未来

序章&#xff1a;牛市来袭&#xff0c;新的探索 新的牛市来临&#xff0c;带来了加密货币世界的一次次惊喜。比特币、以太坊、Solana等生态系统在这场盛宴中展现出各自的独特魅力&#xff0c;带来了一场场引人入胜的探索之旅。让我们跟随着这些生态系统的脚步&#xff0c;一起…
阅读更多...
基础算法前缀和与差分

基础算法前缀和与差分

前言 本次博客会介绍一维和二维的前缀和&#xff0c;以及一维二维差分的基本使用&#xff0c;尽量画图&#xff0c;多使用配合文字 使大家理解&#xff0c;希望有所帮助吧 一维前缀和 问题描述 这里有一个长度为n的数组&#xff0c;我们要算出【2,5】区间的元素和 暴力思…
阅读更多...
Mogdb 5.0新特性：SQL PATCH绑定执行计划

Mogdb 5.0新特性：SQL PATCH绑定执行计划

前言 熟悉Oracle的dba都知道&#xff0c;生产系统出现性能问题时&#xff0c;往往是SQL走错了执行计划&#xff0c;紧急情况下&#xff0c;无法及时修改应用代码&#xff0c;dba可以采用多种方式针对于某类SQL进行执行计划绑定&#xff0c;比如SQL Profile、SPM、SQL Plan Base…
阅读更多...
Linux——网络管理nmcli

Linux——网络管理nmcli

nmcli 不能独立使用&#xff0c;需要对应的服务启动 1. NetworkManager.service 2. 网络配置和服务不相关 3. 通过 nmcl &#xff49; 建立网络配置和网卡之前的映射关系 网卡 简称&#xff1a;nmcli d DEVICE &#xff1a;物理设备 TYPE: 物理设备类型 ethernet 以太网…
阅读更多...
C++设计模式：适配器模式（十四）

C++设计模式：适配器模式（十四）

1、定义与动机 定义&#xff1a;将一个类的接口转换成客户希望的另外一个接口。Adapter模式使得原本由于接口不兼容而不能一起工作的哪些类可以一起工作。 动机&#xff1a; 在软件系统中&#xff0c;由于应用环境的变化&#xff0c;常常需要将“一些现存的对象”放在新的环境…
阅读更多...
强固型工业电脑在码头智能闸口、OCR(箱号识别)、集装箱卡车车载电脑行业应用

强固型工业电脑在码头智能闸口、OCR(箱号识别)、集装箱卡车车载电脑行业应用

集装箱卡车车载电脑应用 背景介绍 针对码头集装箱卡车的调度运用, 结合码头TOS系统设计出了各种平台的车载电脑(VT系列)和车载LED显示屏(VLD系列)&#xff0c;同时提供各种安装支架&#xff0c;把车载电脑固定到狭小的驾驶室中&#xff1b;同时提供了各种天线选择&#xff08;…
阅读更多...
【JVM常见问题总结】

【JVM常见问题总结】

文章目录 jvm介绍jvm内存模型jvm内存分配参数jvm堆中存储对象&#xff1a;对象在堆中创建分配内存过程 jvm 堆垃圾收集器垃圾回收算法标记阶段引用计数算法可达性分析算法 清除阶段标记清除算法复制算法标记压缩算法 实际jvm参数实战jvm调优jvm常用命令常用工具 jvm介绍 Java虚…
阅读更多...
高速公路交通运输大数据平台解决方案

高速公路交通运输大数据平台解决方案

前言 交通运输行业面临着多重挑战。其管控困难&#xff0c;涉及广泛地理范围&#xff0c;导致监控成本高且难以及时响应&#xff1b;同时&#xff0c;行业内数据量大&#xff0c;地理信息数据繁多&#xff0c;缺乏高效的可视化工具来揭示数据规律并优化业务&#xff1b;货运和…
阅读更多...
数据结构——第7章 查找

数据结构——第7章 查找

1 线性表的查找 数据元素和顺序表的定义 typedef struct{KeyType key;InfoType otherinfo; }ElemType; typedef struct{ElemType *R;int length; }SSTable; 1.1 顺序查找 int Search_Seq(SSTable ST,KeyType key){ST.R[0].keykey;for(int iST.length;ST.R[i].key!key;i--);…
阅读更多...
回溯算法-组合问题

回溯算法-组合问题

回溯算法-组合问题 77. 组合 问题描述 给定两个整数 n 和 k&#xff0c;返回范围 [1, n] 中所有可能的 k 个数的组合。 你可以按 任何顺序 返回答案。 示例 1&#xff1a; 输入&#xff1a;n 4, k 2 输出&#xff1a; [[2,4],[3,4],[2,3],[1,2],[1,3],[1,4], ]示例 2&a…
阅读更多...
05集合-CollectionListSet

05集合-CollectionListSet

Collection体系的特点、使用场景总结 如果希望元素可以重复&#xff0c;又有索引&#xff0c;索引查询要快? 用ArrayList集合, 基于数组的。(用的最多) 如果希望元素可以重复&#xff0c;又有索引&#xff0c;增删首尾操作快? 用LinkedList集合, 基于链表的。 如果希望增…
阅读更多...
基于SpringBoot + Vue实现的奖学金管理系统设计与实现+毕业论文+答辩PPT

基于SpringBoot + Vue实现的奖学金管理系统设计与实现+毕业论文+答辩PPT

介绍 角色:管理员、学院负责人、学校负责人、学生 管理员:管理员登录进入高校奖助学金系统的实现可以查看系统首页、个人中心、学生管理、学院负责人管理、学校负责人管理、奖学金类型管理、奖学金申请管理、申请提交管理、系统管理等信息 学院负责人:学院负责人登录系统后&am…
阅读更多...
python3--lxml pytoml.core.TomlError expected_equals报错解决

python3--lxml pytoml.core.TomlError expected_equals报错解决

文章目录 一、问题二. 解决方法&#xff1a;三. 参考&#xff1a;四. 总结 一、问题 在ubuntu的armbian上的python3中安装lxml时报错了 安装命令是 pip3 install lxml报错简略信息如下图 File "/usr/share/python-wheels/pytoml-0.1.2-py2.py3-none-any.whl/pytoml/par…
阅读更多...
nlp（6）--构建找规律模型任务

nlp（6）--构建找规律模型任务

前言 仅记录学习过程&#xff0c;有问题欢迎讨论 包含了两个例子 第一个为5分类任务 第二个为2分类任务 Demo1比Demo2难一点&#xff0c;放上边方便以后看。 练习顺序为 Demo2—>Demo1 代码 DEMO1: """ 自定义一个模型 解决 5分类问题 问题如下&#xf…
阅读更多...
SQL概述

SQL概述

1. SQL的分类 SQL语言在功能上主要分为如下3大类&#xff1a; DDL&#xff08;Data Definition Languages、数据定义语言&#xff09;&#xff0c;这些语句定义了不同的数据库、表、视图、索引等数据库对象&#xff0c;还可以用来创建、删除、修改数据库和数据表的结构。主要…
阅读更多...
2.1K Star微软开源的高质量 iot库

2.1K Star微软开源的高质量 iot库

功能描述 该项目是一个开源的 .NET Core 实现&#xff0c;旨在帮助开发者构建适用于物联网(IoT)设备和场景的应用程序。它提供了与传感器、显示器和输入设备等相互作用所需的 GPIO 引脚、串口等硬件的接口。该仓库包含 System.Device.Gpio 库以及针对各种板卡&#xff08;如 Ra…
阅读更多...
redis底层数据结构之ziplist

redis底层数据结构之ziplist

目录 一、概述二、ziplist结构三、Entry结构四、为什么ZipList特别省内存五、ziplist的缺点 上一篇 redis底层数据结构之SDS 下一篇 明天更新 一、概述 一种连续内存空间存储的顺序数据结构&#xff0c;每个元素可以是字符串或整数。优点:节省内存空间。适用于存储小规模的列表…
阅读更多...
STM32 | USART实战案例

STM32 | USART实战案例

STM32 | 通用同步/异步串行接收/发送器USART带蓝牙(第六天)随着扩展的内容越来越多，很多小伙伴已经忘记了之前的学习内容，然后后面这些都很难理解。STM32合集已在专栏创建，方面大家学习。1、通过电脑串口助手发送数据，控制开发板LED灯 从题目中可以挖掘出，本次使用led、延…
阅读更多...
【Linux文件系统开发】认知篇

【Linux文件系统开发】认知篇

【Linux文件系统开发】认知篇 文章目录 【Linux文件系统开发】认知篇一、文件系统的概念二、文件系统的种类&#xff08;文件管理系统的方法&#xff09;三、分区四、文件系统目录结构五、虚拟文件系统&#xff08;Virtual File System&#xff09;1.概念2.原因3.作用4.总结 一…
阅读更多...
最新文章

Copyright @ 2022~2023