（1）Visio视图：

（2）Verilog代码：

module fsm_cola_plus(clk,reset_n,pi_money_one,pi_money_half,po_cola,po_money);input clk;input reset_n;input pi_money_one;input pi_money_half;output po_cola;output po_money;reg [4:0] state;wire [1:0]pi_money;reg [1:0]po;parameter IDLE      = 5'b00001;parameter HALF      = 5'b00010;parameter ONE       = 5'b00100;parameter ONE_HALF  = 5'b01000;parameter TWO       = 5'b10000;//输入、输出信号编码设计assign pi_money = {pi_money_one,pi_money_half};assign {po_cola,po_money} = po;//状态机状态跳转设计always@(posedge clk or negedge reset_n)if(!reset_n)state <= IDLE;else begincase(state)IDLE:beginif(pi_money == 2'b10)state <= ONE;else if(pi_money == 2'b01)state <= HALF;else state <= state;endHALF:beginif(pi_money == 2'b10)state <= ONE_HALF;else if(pi_money == 2'b01)state <= ONE;else state <= state;endONE:beginif(pi_money == 2'b10)state <= TWO;else if(pi_money == 2'b01)state <= ONE_HALF;else state <= state;endONE_HALF:beginif(pi_money == 2'b10)state <= IDLE;else if(pi_money == 2'b01)state <= TWO;else state <= state;endTWO:beginif((pi_money == 2'b10) || (pi_money == 2'b01))state <= IDLE;else state <= state;enddefault:beginstate <= IDLE;endendcaseend//状态机输出信号设计always@(posedge clk or negedge reset_n)if(!reset_n)po <= 2'b00;else if(((state == ONE_HALF) && (pi_money == 2'b10)) || ((state == TWO) && (pi_money == 2'b01)))po <= 2'b10;else if((state == TWO) && (pi_money == 2'b10))po <= 2'b11;elsepo <= 2'b00;endmodule

（3）仿真文件代码：

`timescale 1ns / 1psmodule fsm_cola_plus_tb;reg clk;reg reset_n;reg pi_money_one;reg pi_money_half;wire po_cola;wire po_money;fsm_cola_plus fsm_cola_plus_inst(.clk(clk),.reset_n(reset_n),.pi_money_one(pi_money_one),.pi_money_half(pi_money_half),.po_cola(po_cola),.po_money(po_money));initial clk = 1'd1;always #10 clk = ~clk;initial beginreset_n <= 1'd0;pi_money_half <= 1'd0;pi_money_one  <= 1'd0;#15;reset_n <= 1'd1;#200;pi_money_half <= 1'd1;      //0.5元#20;pi_money_half <= 1'd0;pi_money_one  <= 1'd1;      //1.5元#20;pi_money_half <= 1'd0;pi_money_one  <= 1'd0;      //1.5元#40;pi_money_half <= 1'd0;pi_money_one  <= 1'd1;      //0元       可乐不找零#20;pi_money_half <= 1'd0;  pi_money_one  <= 1'd0;      //0元#200;pi_money_half <= 1'd0;pi_money_one  <= 1'd1;      //1元#20;pi_money_half <= 1'd1;pi_money_one  <= 1'd0;      //1.5元#20;pi_money_half <= 1'd1;pi_money_one  <= 1'd0;      //2元#20pi_money_half <= 1'd0;pi_money_one  <= 1'd1;      //0元   可乐加找零#20pi_money_half <= 1'd0;pi_money_one  <= 1'd0;      //2元#200;$stop;endendmodule

（4）仿真波形：