题目：
解题：
module top_module(clk,reset,in,out);input clk;input reset;input in;output out;parameter A=0,B=1;reg [1:0]current_state,next_state;always@(posedge clk)beginif(reset)current_state=B;elsecurrent_state=next_state;endalways@(*)begincase(current_state)A:next_state=(in==0)?B:A;B:next_state=(in==0)?A:B;endcaseendassign out=(current_state==A)?0:1;
endmodule
结果正确:
