题目:

解题：

module top_module(input clk,input areset,    // Asynchronous reset to state Binput in,output out);//  parameter A=0, B=1; reg state, next_state;always @(*) begin    // This is a combinational always block// State transition logiccase(state)A:beginif(in==0)next_state=B;elsenext_state=A;endB:beginif(in==0)next_state=A;elsenext_state=B;endendcaseendalways @(posedge clk, posedge areset) begin    // This is a sequential always block// State flip-flops with asynchronous resetif(areset)state<=B;elsestate<=next_state;end// Output logicassign out = (state == A)?0:1;endmodule

结果正确：