名称:四位十进制数字频率计VHDL,quartus仿真
软件:Quartus
语言:VHDL
代码功能:
使用直接测频法测量信号频率,测频范围为1~9999Hz,具有超量程报警功能
演示视频:四位十进制数字频率计VHDL,quartus仿真_Verilog/VHDL资源下载
代码下载:四位十进制数字频率计VHDL,quartus仿真_Verilog/VHDL资源下载名称:四位十进制数字频率计VHDL,quartus仿真(代码在文末付费下载)软件:Quartus语言:VHDL代码功能: 使用直接测频法测量信号频率,测频范围为1~9999Hz,具有超量程报警功能演示视频:部分代码展示LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;--计数器模块ENTIThttp://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=186
FPGA代码资源下载网:hdlcode.com
部分代码展示
LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_unsigned.all; --计数器模块 ENTITY counter ISPORT (signal_in : IN STD_LOGIC;--被测信号en : IN STD_LOGIC;--1S闸门信号rst : IN STD_LOGIC;--复位alarm : OUT STD_LOGIC;--报警number : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)--频率值); END counter; ARCHITECTURE trans OF counter ISSIGNAL num_0 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";SIGNAL num_1 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";SIGNAL num_2 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";SIGNAL num_3 : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000"; BEGINnumber <= (num_3 & num_2 & num_1 & num_0);--单位Hz--计数,计数1s内的信号周期数,计数值就是频率值PROCESS (signal_in, rst)BEGINIF (rst = '1') THENnum_0 <= "0000";num_1 <= "0000";num_2 <= "0000";num_3 <= "0000";alarm <= '0';ELSIF (signal_in'EVENT AND signal_in = '1') THENIF (en = '1') THEN--计数,低位都是9,则高位加1,低位清零,例如加到999,则变为1000IF (num_3 = "1001" AND num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THENnum_0 <= "0000";num_1 <= "0000";num_2 <= "0000";num_3 <= "0000";alarm <= '1';--报警ELSIF (num_2 = "1001" AND num_1 = "1001" AND num_0 = "1001") THENnum_0 <= "0000";num_1 <= "0000";num_2 <= "0000";num_3 <= num_3 + "0001";--低位为9,则高位加1,低位清零alarm <= '0';ELSIF (num_1 = "1001" AND num_0 = "1001") THENnum_0 <= "0000";num_1 <= "0000";num_2 <= num_2 + "0001";--低位为9,则高位加1,低位清零num_3 <= num_3;alarm <= '0';ELSIF (num_0 = "1001") THENnum_0 <= "0000";num_1 <= num_1 + "0001";--低位为9,则高位加1,低位清零num_2 <= num_2;num_3 <= num_3;alarm <= '0';ELSEnum_0 <= num_0 + "0001";--低位加1num_1 <= num_1;num_2 <= num_2;num_3 <= num_3;alarm <= '0';END IF;END IF;END IF;END PROCESS;END trans;
设计文档(文档点击可下载):
1. 工程文件
2. 程序文件
3. 程序编译
4. 仿真图
整体仿真图
计数器模块
锁存器模块
控制模块
产生闸门信号,清零信号,锁存信号
数码管显示模块
设计文档.doc