本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益

---

题目链接：Bugs mux2 - HDLBits

module top_module (input sel,input [7:0] a,input [7:0] b,output [7:0] out  );assign out = sel ? a : b ; endmodule

---

题目链接：Bugs nand3 - HDLBits

module top_module (input a, input b, input c, output out);//wire t ; andgate inst1 ( t, a, b, c, 1, 1 );assign out = ~t ; endmodule

---

题目链接：Bugs mux4 - HDLBits

module top_module (input [1:0] sel,input [7:0] a,input [7:0] b,input [7:0] c,input [7:0] d,output [7:0] out  ); //wire [7:0] mux0, mux1;mux2 m0 ( sel[0],    a,    b, mux0 );mux2 m1 ( sel[0],    c,    d, mux1 );mux2 m2 ( sel[1], mux0, mux1,  out );endmodule

---

题目链接：Bugs addsubz - HDLBits

// synthesis verilog_input_version verilog_2001
module top_module ( input do_sub,input [7:0] a,input [7:0] b,output reg [7:0] out,output reg result_is_zero
);//always @(*) begincase (do_sub)0: out = a+b;1: out = a-b;endcaseif (out == 8'b00000000)result_is_zero = 1;else result_is_zero = 0;endendmodule

---

题目链接：Bugs case - HDLBits

module top_module (input [7:0] code,output reg [3:0] out,output reg valid
);//always @(*) beginvalid = 1 ; out = 0 ; case (code)8'h45: out = 0;8'h16: out = 1;8'h1e: out = 2;8'h26: out = 3;8'h25: out = 4;8'h2e: out = 5;8'h36: out = 6;8'h3d: out = 7;8'h3e: out = 8;8'h46: out = 9;default: valid = 0;endcaseend
endmodule