本篇系列教程介绍总结DC Flow，为了不涉密，在这里以DC labs为Demo做一个入门的介绍；目标：用起来EDA 工具是最基础也是最简单的；重点是如何去分析报告，依据报告指导进行修改；
作为ICer，很多时间都是要看Data sheet或者UG,这个时候看一下先广看一下，通过CSDN或者其他博客，先快速了解各大概，但是不要trapped，还是要回归手册本身。

0 Intro

本着先森林再树木的策略，先从top上介绍一下DC flow的基本流程：

1.拿.synopsys_dc.setup（本质是TCL文件）：
设置path：环境路径；1.除了EDA自带的路径；2.自定义路径：rtl/ ; scripts/ config/
指定lib路径：
给EDA里面专有变量 设置目录路径或者文件路径；
2.用design_vision启动EDA工具，会自定加载上面文件；
3.命令行或者GUI选项读取 rtl文件；可以查看原理图和符号界面；
4.读设计约束文件；
5.编译RTL
6.生成时序面积报告，查看违例；主要是看关键路径的时序；
7.保存编译好的RTL信息文件；

1 DC Demo

1.config the .synopsys_dc.setup for what said above;

set seach_paht "$search_path ../ref/db ./scripts"
set target_library "sc_max.db"
set ling_library "* sc_max.db"
set symbol_library "sc.sdb"

2.Setup design_vision and confirm setup’s cfg
通过输出的echo，可以清晰的看到：
search_path:没有把自定义的文件加载进去，只有工具的目录路径；
这里不管通过echo输出有没有正确输出路径，都要在GUI界面 file–>setup查看一下
在这里再次check发现还是没有自定义的path，在这里手动add一下；
GUI界面里的design_vision本质是一个bash shell.
type the below cmd to confirm again.

printvar target_library  
printvar link_library  
printvar symbol_library  
printvar search_path  
alias

3.read desgin and auto get the rtl hirec top module.
read rtl file ;
select top module and link design;
save the unmapped design in ddc fromat.

write –hier –f ddc –out unmapped/TOP.ddc

4.type cmd for viewing the list of designs and liarbry inside DC;

list_libs
list_designs

5.Expore Symbol and Schemeatic Views
Symbol 和Schemeatic View的概念是2007的，现在的DC版本已经合成一个概念：Schemeatic View，直接支持上面两个；
此时因为还没有编译，链接到目标库，点击Schemeatic生成的schemeatic的是GTECH；GTECH components are generic Boolean gates and registers that represent the generic, non-technology specific functionality of a design.

Conclued : The Basic Steps in Synthesis Flow
The four steps after “read” will be performed in the upcoming tasks:
• Read and translate RTL code (read_vhdl/read_verilog)
• Constrain the design (source a constraints file)
• Synthesize the design (compile)
• Generate reports (report_*)
• Save the resulting netlist (write）
现在已经执行完第一步了，可以得到中间GTECH通用布尔门和寄存器的中间网表文件；
6.Source scripts/constrain
source the xx.con but don’t see how the xxx.con applied to design.

source TOP.con

Will learn how to generate the relevant reports to verify constrains that have been applied to a design.

7.Compile or Map to the Vendor-Specifice Gates
Will see various tables for the different optimization phases of compile;
“AREA” tables：Design size;
“WORST NEG SLACK” : how much the critical or worst path in the design is violating;
“TOTAL NEG SLACK”：The sum of all the violating path slacks.

compile

8.Generate Reports and Analyze Timing

report_constraint -all_violators     //alias for rc
report_timing    //shows the timing of the critical path.
report_area  //ailas for ra  

9.save the Optimized Design
File–save as…
or write cmd…

10.Remove Designs and exit Design Vision

remove_design -designs   //alias for fr
design_vision -f scripts/run_history.tcl //for recreate everything;exit  //for exit the design_vision

11.learn how to use doc online

If do it here, You have mastered the basic DC tool.