根据RTL图编写Verilog程序

题目描述
根据以下RTL图，使用 Verilog HDL语言编写代码，实现相同的功能，并编写testbench验证功能。

`timescale 1ns/1nsmodule RTL(input clk,input rst_n,input data_in,output reg data_out);reg data_in_reg;always@(posedge clk or negedge rst_n)beginif(!rst_n)data_in_reg <= 1'b0;else data_in_reg <= data_in;endwire data_in_ir;assign data_in_ir = data_in & (~data_in_reg);always@(posedge clk or negedge rst_n)beginif(!rst_n)data_out <= 1'b0;elsedata_out <= data_in_ir;endendmodule