lut6

A B 每个3bit， 使用一个lut
https://github.com/Xilinx/Vitis-Tutorials/blob/2023.2/AI_Engine_Development/AIE/Design_Tutorials/03-beamforming/Module_03_PL_Design/dlbf_data/hdl/dlbf_data_ram2axis_64b.v

reg [15:0] addrb=16'd0;(* KEEP = "TRUE" *) wire addrb_cmp0;(* KEEP = "TRUE" *) wire addrb_cmp1;(* KEEP = "TRUE" *) wire addrb_cmp2;(* KEEP = "TRUE" *) wire addrb_cmp3;(* KEEP = "TRUE" *) wire addrb_cmp4;(* KEEP = "TRUE" *) wire addrb_cmp5;wire addrb_rst;assign addrb_cmp0 = addrb[2:0]==rollover_addr_minus1[2:0];assign addrb_cmp1 = addrb[5:3]==rollover_addr_minus1[5:3];assign addrb_cmp2 = addrb[8:6]==rollover_addr_minus1[8:6];assign addrb_cmp3 = addrb[11:9]==rollover_addr_minus1[11:9];assign addrb_cmp4 = addrb[14:12]==rollover_addr_minus1[14:12];assign addrb_cmp5 = addrb[15:15]==rollover_addr_minus1[15:15];assign addrb_rst = &{addrb_cmp0,addrb_cmp1,addrb_cmp2,addrb_cmp3,addrb_cmp4,addrb_cmp5};