KEEP_HIERACHY指示工具保留用户层次结构，以便优化不会
跨越其边界。虽然这有助于布局规划、分析和调试，但它
会抑制优化，导致更大、更慢的设计。
建议：为了避免这些负面影响，请注册一个模块实例的所有输出，其中
KEEP_HIERACHY附后。为了达到最佳效果，请在合成之前应用此属性。
KEEP_HIERACHY用于防止沿层次结构边界进行优化。这个
Vivado合成工具试图保持RTL中指定的相同的通用层次结构，
但为了提高结果质量（QoR），它可以使其变平或修改。
如果将KEEP_HIERACHY放置在实例上，则合成工具会将边界保持在该实例上
水平静态。这可能会影响QoR，也不应用于描述
3态输出和I/O缓冲器的控制逻辑。KEEP_HIERACHY可以放置在
模块或架构级别，
Architecture Support
All architectures.
Applicable Objects
• Hierarchical modules ( get_cells )
Values
• TRUE : Preserves the hierarchy by not allowing optimization across the hierarchy
boundary.
• FALSE : Allows optimization across the hierarchy (default).
Syntax
Verilog Syntax
Place the Verilog attribute immediately before the user hierarchy instantiation:
(* KEEP_HIERARCHY = "{TRUE|FALSE}" *)
Verilog Syntax Example
// Preserve the hierarchy of instance CLK1_rst_sync
(* KEEP_HIERARCHY = "TRUE" *) reset_sync #(
.STAGES(5)
) CLK1_rst_sync (
.RST_IN(RST | ~LOCKED),
.CLK(clk1_100mhz),
.RST_OUT(rst_clk1)
);
On Module:
(* keep_hierarchy = "yes" *) module bottom (in1, in2, in3, in4, out1, out2);
On Instance:
(* keep_hierarchy = "yes" *)bottom u0 (.in1(in1), .in2(in2), .out1(temp1));
VHDL Syntax
Declare the VHDL attribute as follows:
attribute KEEP_HIERARCHY : string;
Specify the VHDL attribute as follows:
attribute KEEP_HIERACHRY of name: label is "{TRUE|FALSE}";
Where
• name is the instance name of a user defined instance.
VHDL Syntax Example
attribute KEEP_HIERARCHY : string;
-- Preserve the hierarchy of instance CLK1_rst_sync
attribute KEEP_HIERARCHY of CLK1_rst_sync: label is "TRUE";
…
CLK1_rst_sync : reset_sync
PORT MAP (
RST_IN => RST_LOCKED,
CLK => clk1_100mhz,
RST_OUT => rst_clk1
);
On a module:
attribute keep_hierarchy : string;
attribute keep_hierarchy of beh : architecture is "yes";
On an instance:
attribute keep_hierarchy : string;
attribute keep_hierarchy of u0 : label is "yes";
XDC Syntax
set_property KEEP_HIERARCHY {TRUE|FALSE} [get_cells instance_name]
Where
• instance_name is a hierarchical module.
XDC Syntax Example
# Preserve the hierarchy of instance CLK1_rst_sync
set_property KEEP_HIERARCHY TRUE [get_cells CLK1_rst_sync]
