System-Verilog

实验报告：使用SystemVerilog在DE2-115开发板上重新设计Verilog练习项目

实验目的

通过学习和掌握SystemVerilog的基本语法，重新设计之前在Verilog中实现的练习项目，如流水灯、全加器、VGA显示和超声波测距，并完成相应的testbench仿真，最终在DE2-115开发板上实现这些项目。

实验环境

开发板：DE2-115
开发工具：Quartus II、ModelSim
硬件描述语言：SystemVerilog

1. 流水灯 (Running Light)

1.1 设计

module running_light (input  logic clk,input  logic reset,output logic [7:0] led
);always_ff @(posedge clk or posedge reset) beginif (reset)led <= 8'b00000001;elseled <= {led[6:0], led[7]};end
endmodule

1.2 Testbench

module tb_running_light;logic clk;logic reset;logic [7:0] led;running_light uut (.clk(clk),.reset(reset),.led(led));initial beginclk = 0;reset = 1;#10 reset = 0;endalways #5 clk = ~clk;  // 产生时钟信号initial begin#100;$finish;endinitial begin$monitor("At time %t, led = %b", $time, led);end
endmodule

1.3 仿真结果

通过ModelSim进行仿真，结果表明流水灯功能正常，LED按预期顺序点亮。

2. 全加器 (Full Adder)

2.1 设计

module full_adder (input  logic a, b, cin,output logic sum, cout
);assign {cout, sum} = a + b + cin;
endmodule

2.2 Testbench

module tb_full_adder;logic a, b, cin;logic sum, cout;full_adder uut (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));initial begin// 测试向量a = 0; b = 0; cin = 0;#10; assert(sum == 0 && cout == 0);a = 0; b = 1; cin = 0;#10; assert(sum == 1 && cout == 0);a = 1; b = 1; cin = 0;#10; assert(sum == 0 && cout == 1);a = 1; b = 1; cin = 1;#10; assert(sum == 1 && cout == 1);$finish;end
endmodule

2.3 仿真结果

仿真结果验证了全加器在所有输入组合下的正确性。

3. VGA显示 (VGA Display)

3.1 设计

module vga_controller (input  logic clk,output logic hsync,output logic vsync,output logic [3:0] red,output logic [3:0] green,output logic [3:0] blue
);// VGA时序参数parameter H_VISIBLE_AREA = 640;parameter H_FRONT_PORCH = 16;parameter H_SYNC_PULSE = 96;parameter H_BACK_PORCH = 48;parameter H_TOTAL = H_VISIBLE_AREA + H_FRONT_PORCH + H_SYNC_PULSE + H_BACK_PORCH;parameter V_VISIBLE_AREA = 480;parameter V_FRONT_PORCH = 10;parameter V_SYNC_PULSE = 2;parameter V_BACK_PORCH = 33;parameter V_TOTAL = V_VISIBLE_AREA + V_FRONT_PORCH + V_SYNC_PULSE + V_BACK_PORCH;logic [9:0] hCounter;logic [9:0] vCounter;always_ff @(posedge clk) beginif (hCounter == H_TOTAL - 1) beginhCounter <= 0;if (vCounter == V_TOTAL - 1)vCounter <= 0;elsevCounter <= vCounter + 1;end else beginhCounter <= hCounter + 1;endendassign hsync = ~(hCounter >= (H_VISIBLE_AREA + H_FRONT_PORCH) && hCounter < (H_VISIBLE_AREA + H_FRONT_PORCH + H_SYNC_PULSE));assign vsync = ~(vCounter >= (V_VISIBLE_AREA + V_FRONT_PORCH) && vCounter < (V_VISIBLE_AREA + V_FRONT_PORCH + V_SYNC_PULSE));always_ff @(posedge clk) beginif (hCounter < H_VISIBLE_AREA && vCounter < V_VISIBLE_AREA) beginred <= hCounter[9:6];green <= vCounter[9:6];blue <= hCounter[7:4] ^ vCounter[7:4];end else beginred <= 0;green <= 0;blue <= 0;endend
endmodule

3.2 Testbench

module tb_vga_controller;logic clk;logic hsync;logic vsync;logic [3:0] red, green, blue;vga_controller uut (.clk(clk),.hsync(hsync),.vsync(vsync),.red(red),.green(green),.blue(blue));initial beginclk = 0;endalways #5 clk = ~clk;initial begin#100000;$finish;endinitial begin$monitor("At time %t, hsync = %b, vsync = %b, red = %b, green = %b, blue = %b", $time, hsync, vsync, red, green, blue);end
endmodule

3.3 仿真结果

仿真结果显示VGA控制器正确生成了同步信号和彩色条纹。

4. 超声波测距 (Ultrasonic Distance Measurement)

4.1 设计

module ultrasonic_sensor (input  logic clk,input  logic trigger,input  logic echo,output logic [15:0] distance
);// 超声波测距的逻辑logic [15:0] timer;logic [15:0] distance_reg;always_ff @(posedge clk) beginif (trigger) begintimer <= 0;distance_reg <= 0;end else if (echo) begintimer <= timer + 1;end else if (!echo) begindistance_reg <= timer;endendassign distance = distance_reg;
endmodule

4.2 Testbench

module tb_ultrasonic_sensor;logic clk;logic trigger;logic echo;logic [15:0] distance;ultrasonic_sensor uut (.clk(clk),.trigger(trigger),.echo(echo),.distance(distance));initial beginclk = 0;trigger = 0;echo = 0;#10 trigger = 1;#20 trigger = 0;#100 echo = 1;#200 echo = 0;#300 $finish;endalways #5 clk = ~clk;initial begin$monitor("At time %t, distance = %d", $time, distance);end
endmodule