两种思路
module encoder_83(input [7:0] I ,input EI ,output wire [2:0] Y ,output wire GS ,output wire EO
);reg [4:0] temp1 ;
always @(*) begincasex({EI,I}) 9'b0_xxxx_xxxx:begin temp1 = 5'b000_0_0;end9'b1_0000_0000:begin temp1 = 5'b000_0_1;end9'b1_1xxx_xxxx:begin temp1 = 5'b111_1_0;end9'b1_01xx_xxxx:begin temp1 = 5'b110_1_0;end9'b1_001x_xxxx:begin temp1 = 5'b101_1_0;end9'b1_0001_xxxx:begin temp1 = 5'b100_1_0;end9'b1_0000_1xxx:begin temp1 = 5'b011_1_0;end9'b1_0000_01xx:begin temp1 = 5'b010_1_0;end9'b1_0000_001x:begin temp1 = 5'b001_1_0;end9'b1_0000_0001:begin temp1 = 5'b000_1_0;endendcase
endassign {Y,GS,EO} =temp1;
// assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);
// assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
// assign Y[2] = EI && (I[4] | I[5] | I[6] | I[7]) ;// assign GS = EI && (I[0] | I[1] | I[2] | I[3]| I[4]| I[5]| I[6]| I[7]) ;
// assign EO = EI && ~(I[0] | I[1] | I[2] | I[3]| I[4]| I[5]| I[6]| I[7]) ;endmodule
module encoder_83(input [7:0] I ,input EI ,output wire [2:0] Y ,output wire GS ,output wire EO
);//reg [4:0] temp1 ;
//always @(*) begin
// casex({EI,I})
// 9'b0_xxxx_xxxx:begin temp1 = 5'b000_0_0;end
// 9'b1_0000_0000:begin temp1 = 5'b000_0_1;end
// 9'b1_1xxx_xxxx:begin temp1 = 5'b111_1_0;end
// 9'b1_01xx_xxxx:begin temp1 = 5'b110_1_0;end
// 9'b1_001x_xxxx:begin temp1 = 5'b101_1_0;end
// 9'b1_0001_xxxx:begin temp1 = 5'b100_1_0;end
// 9'b1_0000_1xxx:begin temp1 = 5'b011_1_0;end
// 9'b1_0000_01xx:begin temp1 = 5'b010_1_0;end
// 9'b1_0000_001x:begin temp1 = 5'b001_1_0;end
// 9'b1_0000_0001:begin temp1 = 5'b000_1_0;end
// endcase
//end//assign {Y,GS,EO} =temp1;assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);assign Y[2] = EI && (I[4] | I[5] | I[6] | I[7]) ;assign GS = EI && (I[0] | I[1] | I[2] | I[3]| I[4]| I[5]| I[6]| I[7]) ;assign EO = EI && ~(I[0] | I[1] | I[2] | I[3]| I[4]| I[5]| I[6]| I[7]) ;endmodule